public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
// lowest bank is fixed, but is still effected by mode
SetCDLROM(flags, addr);
}
else if (addr < 0x8000)
{
SetCDLROM(flags, (addr - 0x4000) + ROM_bank * 0x4000);
}
else
{
if (!regs_enable)
{
if (/*RAM_enable && */ (((addr - 0xA000) + RAM_bank * 0x2000) < Core.cart_RAM.Length))
{
SetCDLRAM(flags, (addr - 0xA000) + RAM_bank * 0x2000);
}
else
{
return;
}
}
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
SetCDLROM(flags, addr);
}
else if (addr < 0x8000)
{
SetCDLROM(flags, (addr - 0x4000) + ROM_bank * 0x4000);
}
else if (addr < 0xA000)
{
return;
}
else if (addr < 0xB000)
{
if (RAM_enable_1 && RAM_enable_2)
{
return;
}
else
{
return;
}
}
else
{
return;
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
SetCDLROM(flags, addr);
}
else if (addr < 0x8000)
{
SetCDLROM(flags, (addr - 0x4000) + ROM_bank * 0x4000);
}
else
{
if (Core.cart_RAM != null)
{
if (RAM_enable && (((addr - 0xA000) + RAM_bank * 0x2000) < Core.cart_RAM.Length))
{
SetCDLRAM(flags, (addr - 0xA000) + RAM_bank * 0x2000);
}
else
{
return;
}
}
else
{
return;
}
}
}
public void SetCDL(LR35902.eCDLogMemFlags flags, string type, int cdladdr)
{
if (type == null)
{
return;
}
byte val = (byte)flags;
_cdl[type][cdladdr] |= (byte)flags;
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x8000)
{
SetCDLROM(flags, ROM_bank * 0x8000 + addr);
}
else
{
return;
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
SetCDLROM(flags, addr);
}
else if (addr < 0x8000)
{
SetCDLROM(flags, (addr - 0x4000) + ROM_bank * 0x4000);
}
else
{
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
// lowest bank is fixed
SetCDLROM(flags, addr);
}
else if (addr < 0x8000)
{
SetCDLROM(flags, (addr - 0x4000) + ROM_bank * 0x4000);
}
else
{
return;
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x8000)
{
SetCDLROM(flags, addr);
}
else
{
if (Core.cart_RAM != null)
{
SetCDLRAM(flags, addr - 0xA000);
}
else
{
return;
}
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
// header is scrambled
if ((addr >= 0x100) && (addr < 0x200))
{
int temp0 = (addr & 1);
int temp1 = (addr & 2);
int temp4 = (addr & 0x10);
int temp6 = (addr & 0x40);
temp0 = temp0 << 6;
temp1 = temp1 << 3;
temp4 = temp4 >> 3;
temp6 = temp6 >> 6;
addr &= 0x1AC;
addr |= (ushort)(temp0 | temp1 | temp4 | temp6);
}
if (locked_GBC)
{
addr |= 0x80;
}
SetCDLROM(flags, addr + BASE_ROM_Bank * 0x4000);
}
else if (addr < 0x8000)
{
int temp_bank = (ROM_bank & ~ROM_bank_mask) | (ROM_bank_mask & BASE_ROM_Bank);
temp_bank &= ROM_mask;
SetCDLROM(flags, (addr - 0x4000) + temp_bank * 0x4000);
}
else
{
return;
}
}
public override void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x4000)
{
// lowest bank is fixed, but is still effected by mode
if (sel_mode)
{
SetCDLROM(flags, (ROM_bank & 0x60) * 0x4000 + addr);
}
else
{
SetCDLROM(flags, addr);
}
}
else if (addr < 0x8000)
{
SetCDLROM(flags, (addr - 0x4000) + ROM_bank * 0x4000);
}
else
{
if (Core.cart_RAM != null)
{
if (RAM_enable && (((addr - 0xA000) + RAM_bank * 0x2000) < Core.cart_RAM.Length))
{
SetCDLRAM(flags, (addr - 0xA000) + RAM_bank * 0x2000);
}
else
{
return;
}
}
else
{
return;
}
}
}
void CDLCpuCallback(ushort addr, LR35902.eCDLogMemFlags flags)
{
if (addr < 0x8000)
{
//don't record writes to the ROM, it's just noisy
//NOTE: in principle a mapper could mount a useful resource here, but I doubt it)
if ((flags & LR35902.eCDLogMemFlags.Write) != 0)
{
return;
}
}
if (L.ppu.DMA_start)
{
// some of gekkio's tests require these to be accessible during DMA
if (addr < 0x8000)
{
if (L.ppu.DMA_addr < 0x80)
{
return;
}
else
{
L.mapper.MapCDL(addr, flags);
return;
}
}
else if ((addr >= 0xE000) && (addr < 0xF000))
{
SetCDL(flags, "WRAM", addr - 0xE000);
}
else if ((addr >= 0xF000) && (addr < 0xFE00))
{
SetCDL(flags, "WRAM", (L.RAM_Bank * 0x1000) + (addr - 0xF000));
}
else if ((addr >= 0xFE00) && (addr < 0xFEA0) && L.ppu.DMA_OAM_access)
{
return;
}
else if ((addr >= 0xFF00) && (addr < 0xFF80)) // The game GOAL! Requires Hardware Regs to be accessible
{
return;
}
else if ((addr >= 0xFF80))
{
SetCDL(flags, "HRAM", addr - 0xFF80);
}
}
if (addr < 0x900)
{
if (addr < 0x100)
{
// return Either BIOS ROM or Game ROM
if ((L.GB_bios_register & 0x1) == 0)
{
return;
}
else
{
L.mapper.MapCDL(addr, flags);
return;
}
}
else if (addr >= 0x200)
{
// return Either BIOS ROM or Game ROM
if (((L.GB_bios_register & 0x1) == 0) && L.is_GBC)
{
return;
}
else
{
L.mapper.MapCDL(addr, flags);
return;
}
}
else
{
L.mapper.MapCDL(addr, flags);
return;
}
}
else if (addr < 0x8000)
{
L.mapper.MapCDL(addr, flags);
return;
}
else if (addr < 0xA000)
{
return;
}
else if (addr < 0xC000)
{
L.mapper.MapCDL(addr, flags);
return;
}
else if (addr < 0xD000)
{
return;
}
else if (addr < 0xE000)
{
SetCDL(flags, "WRAM", (L.RAM_Bank * 0x1000) + (addr - 0xD000));
}
else if (addr < 0xF000)
{
SetCDL(flags, "WRAM", addr - 0xE000);
}
else if (addr < 0xFE00)
{
SetCDL(flags, "WRAM", (L.RAM_Bank * 0x1000) + (addr - 0xF000));
}
else if (addr < 0xFEA0)
{
return;
}
else if (addr < 0xFF00)
{
return;
}
else if (addr < 0xFF80)
{
return;
}
else if (addr < 0xFFFF)
{
SetCDL(flags, "HRAM", addr - 0xFF80);
}
else
{
return;
}
}
protected void SetCDLRAM(LR35902.eCDLogMemFlags flags, int cdladdr)
{
Core.SetCDL(flags, "CartRAM", cdladdr);
}
public virtual void MapCDL(ushort addr, LR35902.eCDLogMemFlags flags)
{
}
