protected BaseRiscV(CoreLevelInterruptor clint, uint hartId, string cpuType, Machine machine, PrivilegeArchitecture privilegeArchitecture, Endianess endianness, CpuBitness bitness) : base(cpuType, machine, endianness, bitness)
{
HartId = hartId;
clint.RegisterCPU(this);
this.clint = clint;
this.privilegeArchitecture = privilegeArchitecture;
var architectureSets = DecodeArchitecture(cpuType);
foreach (var @set in architectureSets)
{
if (Enum.IsDefined(typeof(InstructionSet), set))
{
TlibAllowFeature((uint)set);
}
else if ((int)set == 'G' - 'A')
{
//G is a wildcard denoting multiple instruction sets
foreach (var gSet in new[] { InstructionSet.I, InstructionSet.M, InstructionSet.F, InstructionSet.D, InstructionSet.A })
{
TlibAllowFeature((uint)gSet);
}
}
else
{
this.Log(LogLevel.Warning, $"Undefined instruction set: {char.ToUpper((char)(set + 'A'))}.");
}
}
TlibSetPrivilegeArchitecture109(privilegeArchitecture == PrivilegeArchitecture.Priv1_09 ? 1 : 0u);
}
public RiscV64(CoreLevelInterruptor clint, string cpuType, Machine machine, uint hartId = 0, PrivilegeArchitecture privilegeArchitecture = PrivilegeArchitecture.Priv1_10, Endianess endianness = Endianess.LittleEndian) : base(clint, hartId, cpuType, machine, privilegeArchitecture, endianness, CpuBitness.Bits64)
{
}
