public override PowerPcInstruction Decode(uint wInstr, PowerPcDisassembler dasm) { // Only supported on 64-bit arch. if (dasm.defaultWordWidth.BitSize == 32) { return(dasm.CreateInvalidInstruction()); } else { Mnemonic mnemonic; switch ((wInstr >> 1) & 0xF) { case 0: case 1: mnemonic = Mnemonic.rldicl; break; case 2: case 3: mnemonic = Mnemonic.rldicr; break; case 4: case 5: mnemonic = Mnemonic.rldic; break; case 6: case 7: mnemonic = Mnemonic.rldimi; break; case 8: mnemonic = Mnemonic.rldcl; break; case 9: mnemonic = Mnemonic.rldcr; break; default: return(dasm.CreateInvalidInstruction()); } wInstr &= ~1u; return(new PowerPcInstruction(mnemonic) { InstructionClass = InstrClass.Linear, Operands = new MachineOperand[] { dasm.RegFromBits(wInstr >> 16), dasm.RegFromBits(wInstr >> 21), ImmediateOperand.Byte((byte)((wInstr >> 11) & 0x1F | (wInstr << 4) & 0x20)), ImmediateOperand.Byte((byte)((wInstr >> 6) & 0x1F | (wInstr & 0x20))), } }); } }
public override PowerPcInstruction Decode(PowerPcDisassembler dasm, uint wInstr) { // Only supported on 64-bit arch. if (dasm.defaultWordWidth.BitSize == 32) { return(new PowerPcInstruction(Opcode.illegal)); } else { Opcode opcode; switch ((wInstr >> 1) & 0xF) { case 0: case 1: opcode = Opcode.rldicl; break; case 2: case 3: opcode = Opcode.rldicr; break; case 4: case 5: opcode = Opcode.rldic; break; case 6: case 7: opcode = Opcode.rldimi; break; case 8: opcode = Opcode.rldcl; break; case 9: opcode = Opcode.rldcr; break; default: return(new PowerPcInstruction(Opcode.illegal)); } wInstr &= ~1u; return(new PowerPcInstruction(opcode) { iclass = InstrClass.Linear, op1 = dasm.RegFromBits(wInstr >> 16), op2 = dasm.RegFromBits(wInstr >> 21), op3 = ImmediateOperand.Byte((byte)((wInstr >> 11) & 0x1F | (wInstr << 4) & 0x20)), op4 = ImmediateOperand.Byte((byte)((wInstr >> 6) & 0x1F | (wInstr & 0x20))), }); } }