/// <summary>
/// Things ctrl done every cycle.
/// </summary>
public static void Step()
{
cycle++;
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine();
DEBUG.WriteLine("---------PIM Memory Controller [" + id + "] Update [Cycle " + cycle + "]------------");
}
for (int i = 0; i < wait_queue.Count(); i++)
{
ProcRequest peek = wait_queue[i];
if (peek.cycle + (UInt64)Config.mc_latency <= cycle - 1)
{
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine("-- Issue ProcRequest : [" + peek.type + "] [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]");
}
if (PIMConfigs.Consistency_Model == Consistency.SpinLock)
{
//if (Config.DEBUG_MTRL)
// DEBUG.WriteLine("-- Use Coherence : [" + Config.pim_config.Consistency_Model.ToString() + "]");
Coherence.spin_lock.setlock(peek.actual_addr);
//when pim units start to perform, flush all relative data in the host core
if (!Coherence.flush(peek.block_addr))
{
Coherence.spin_lock.relese_lock(peek.actual_addr);
DEBUG.WriteLine("-- Waiting Host cores flushing data : [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]");
continue;
}
send_queue[MemorySelector.get_id(wait_queue[i].actual_addr)].Enqueue(transfer(wait_queue[i]));
wait_queue.RemoveAt(i);
i--;
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine("-- Sent ProcRequest : [" + peek.type + "] [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]");
}
}
}
}
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine();
}
}
/// <summary>
/// try to store data to target address
/// </summary>
/// <returns></returns>
public override bool read_input()
{
if (status == Status.Complete)
{
//store complete
intermid = input;
input_ready = false;
input = null;
status = Status.NoOP;
return(true);
}
if (status == Status.NoOP)
{
//currently no operations
if (input_ready && input != null)
{
if (Coherence.consistency == Consistency.SpinLock)
{
//lock target address
Coherence.spin_lock.setlock((UInt64)input);
// try to flush data in host core
if (!Coherence.flush((UInt64)input, true))
{
Coherence.spin_lock.relese_lock((UInt64)input);
DEBUG.WriteLine("-- Waiting Host cores flushing data : [0x" + ((UInt64)input).ToString("X") + "]");
stall = true;
return(false);
}
}
if (PIMConfigs.memory_method == PIM_Load_Method.Bypass)
{
//bypass mode :store only cost latency cycles
latency--;
if (latency == 0)
{
intermid = input;
input_ready = false;
input = null;
return(true);
}
stall = true;
return(false);
}
else
{
//try to add store request to PIM memory controller
PIMRequest req = new PIMRequest();
req.actual_addr = (UInt64)input;
req.cycle = GlobalTimer.tick;
req.if_mem = true;
req.pid = (Parent as ComputationalUnit).id;
req.stage_id.Add(this.id);
req.type = RequestType.STORE;
PIMMctrl.add_to_mctrl(req);
status = Status.Outstanding;
stall = true;
return(false);
}
}
return(false);
}
//at this time, pipeline is waitting for store callback of memoryobjects.
stall = true;
return(false);
}
public override bool read_input()
{
if (status == Status.Complete)
{
intermid = input;
input_ready = false;
input = null;
status = Status.NoOP;
return(true);
}
if (status == Status.NoOP)
{
if (input_ready && input != null)
{
if (Coherence.consistency == Consistency.SpinLock)
{
Coherence.spin_lock.setlock((UInt64)input);
if (!Coherence.flush((UInt64)input, true))
{
Coherence.spin_lock.relese_lock((UInt64)input);
DEBUG.WriteLine("-- Waiting Host cores flushing data : [0x" + ((UInt64)input).ToString("X") + "]");
stall = true;
return(false);
}
}
if (PIMConfigs.memory_method == PIM_Load_Method.Bypass)
{
latency--;
if (latency == 0)
{
intermid = input;
input_ready = false;
input = null;
return(true);
}
return(false);
}
else
{
PIMRequest req = new PIMRequest();
req.actual_addr = (UInt64)input;
req.cycle = GlobalTimer.tick;
req.if_mem = true;
req.pid = (Parent as ComputationalUnit).id;
req.stage_id.Add(this.id);
req.type = RequestType.LOAD;
PIMMctrl.add_to_mctrl(req);
status = Status.Outstanding;
stall = true;
return(false);
}
}
return(false);
}
stall = true;
return(false);
}
