Beispiel #1
0
        static Stat()
        {
            for (uint i = 0; i < procs.Length; i++)
            {
                procs[i] = new ProcStat();
            }
            for (uint i = 0; i < mctrls.Length; i++)
            {
                mctrls[i] = new MemCtrlStat(i);
            }
            for (uint i = 0; i < busses.Length; i++)
            {
                busses[i] = new BusStat(i);
            }

            for (uint c = 0; c < Config.mem.channel_max; c++)
            {
                scheds[c] = new MemSchedStat();
                for (uint r = 0; r < Config.mem.rank_max; r++)
                {
                    for (uint b = 0; b < 8; b++)
                    {
                        banks[c, r, b] = new BankStat(c, r, b);
                    }
                }
            }
        }
Beispiel #2
0
        public int tick()
        {        //Clock in RBLA, make decision when Cycles is multiples of Interval
            //If Migration



            if (target)
            {
                //	Console.WriteLine("Info------------");
                //	Console.WriteLine(target_req.addr.bid);
                //Console.WriteLine(target_req.addr.cid);
                BankStat bank_stat = Stat.banks2[target_req.addr.cid, target_req.addr.rid, target_req.addr.bid];

                //Console.WriteLine(bank_stat.access.Count);
            }



            if (Cycles == 0)
            {
                if (Config.proc.cache_insertion_policy == "RBLA")
                {
                    RBLA.initialize();
                }
                else if (Config.proc.cache_insertion_policy == "PFA")
                {
                    PFA.initialize();
                }
            }
            else
            {
                if (Cycles % Interval == 0)
                {
                    MigrationDecision();
                }
                if (target)
                {
                    target = false;
                    if (Config.proc.cache_insertion_policy == "RBLA")
                    {
                        RBLA.tick();
                    }
                    else if (Config.proc.cache_insertion_policy == "PFA" && Cycles >= Interval)
                    {
                        PFA.tick();
                    }
                }
                if (Cycles % Interval == 0)
                {
                    RowStat.ClearPerInterval();
                }
            }
            Migration.tick();
            Cycles++;
            return(0);
        }
Beispiel #3
0
        private void issue_cmd(Cmd cmd)
        {
            MemAddr addr = cmd.addr;

            List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];

            Dbg.Assert(cmd == cmd_q[0]);
            cmd_q.RemoveAt(0);
            BankStat bank_stat = Stat.banks[addr.cid, addr.rid, addr.bid];
            BusStat  bus_stat  = Stat.busses[addr.cid];

            //writeback mode stats
            if (wb_mode)
            {
                if (cmd.type == Cmd.TypeEnum.READ)
                {
                    rds_per_wb_mode++;
                }
                else if (cmd.type == Cmd.TypeEnum.WRITE)
                {
                    wbs_per_wb_mode++;
                }
            }

            //string dbg;
            switch (cmd.type)
            {
            case Cmd.TypeEnum.ACTIVATE:
                activate(addr);

                /*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
                //stats
                bank_stat.cmd_activate.Collect();
                bank_stat.utilization.Collect(timing.tRCD);

                //shadow row-buffer id
                meta_mctrl.sched.count_queueing(cmd, pid_rowid_per_procrankbank[addr.rid, addr.bid]);
                shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid;
                rowid_per_procrankbank[addr.rid, addr.bid]     = addr.rowid;
                pid_rowid_per_procrankbank[addr.rid, addr.bid] = cmd.req.pid;
                break;

            case Cmd.TypeEnum.PRECHARGE:
                precharge(addr);

                /*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
                //stats
                bank_stat.cmd_precharge.Collect();
                bank_stat.utilization.Collect(timing.tRP);
                break;

            case Cmd.TypeEnum.READ:
                read(addr, cmd.req.pid);

                /*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/

                //writeback mode
                if (wb_mode && cmd.is_drain)
                {
                    Dbg.Assert(reads_to_drain > 0);
                    reads_to_drain--;
                }

                //stats
                bank_stat.cmd_read.Collect();
                bank_stat.utilization.Collect(timing.tCL);
                bus_stat.access.Collect();
                bus_stat.utilization.Collect(timing.tBL);
//                    Console.Write("HERE\n");
                meta_mctrl.sched.bus_interference_count(cmd);
                break;

            case Cmd.TypeEnum.WRITE:
                write(addr, cmd.req.pid);

                //writeback mode
                if (!wb_mode && cmd.is_drain)
                {
                    Dbg.Assert(writes_to_drain > 0);
                    writes_to_drain--;
                }
                else
                {
                    mwbmode.issued_write_cmd(cmd);
                }

                //stats
                bank_stat.cmd_write.Collect();
                bank_stat.utilization.Collect(timing.tCL);
                bus_stat.access.Collect();
                bus_stat.utilization.Collect(timing.tBL);
                break;

            default:
                //should never get here
                throw new System.Exception("DRAM: Invalid Cmd.");
            }
            //Debug.WriteLine(dbg);
        }
Beispiel #4
0
        private void issue_req(Req req)
        {
            //remove request from waiting queue
            List <Req> q = get_q(req);

            Dbg.Assert(q.Contains(req));
            q.Remove(req);

            req.queueing_latency             = (int)(cycles - req.ts_arrival);
            total_queueing_latency[req.pid] += (ulong)req.queueing_latency;
            if (Sim.highest_rank_proc == req.pid)
            {
                Sim.procs[req.pid].queueing_latency += (ulong)req.queueing_latency;
            }
            Stat.mctrls[cid].queueing_latency_per_proc[req.pid].Collect(req.queueing_latency);

            //add to inflight queue
            MemAddr    addr       = req.addr;
            List <Req> inflight_q = inflightqs[addr.rid, addr.bid];

            Dbg.Assert(inflight_q.Count < inflight_q.Capacity);
            inflight_q.Add(req);

            //add to command queue
            List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];

            Dbg.Assert(cmd_q.Count == 0);
            List <Cmd> new_cmd_q = decode_req(req);

            Dbg.Assert(new_cmd_q.Count > 0);
            cmd_q.AddRange(new_cmd_q);
            Cmd cmd = cmd_q[0];


            //meta_mctrl
            meta_mctrl.issue_req(req);

            req.ts_issue = cycles;

            //stats
            BankStat bstat = Stat.banks[addr.cid, addr.rid, addr.bid];

            bstat.access.Collect();
            if (cmd.type == Cmd.TypeEnum.PRECHARGE || cmd.type == Cmd.TypeEnum.ACTIVATE)
            {
                //bank stat
                bstat.row_miss.Collect();
                bstat.row_miss_perproc[req.pid].Collect();

                //proc stat
                if (cmd.req.type == ReqType.RD)
                {
                    Stat.procs[req.pid].row_hit_rate_read.Collect(0);
                    Stat.procs[req.pid].row_miss_read.Collect();
                }
                else
                {
                    Stat.procs[req.pid].row_hit_rate_write.Collect(0);
                    Stat.procs[req.pid].row_miss_write.Collect();
                }
            }
            else
            {
                //bank stat
                bstat.row_hit.Collect();
                bstat.row_hit_perproc[req.pid].Collect();

                //proc stat
                if (cmd.req.type == ReqType.RD)
                {
                    Stat.procs[req.pid].row_hit_rate_read.Collect(1);
                    Stat.procs[req.pid].row_hit_read.Collect();
                }
                else
                {
                    Stat.procs[req.pid].row_hit_rate_write.Collect(1);
                    Stat.procs[req.pid].row_hit_write.Collect();
                }
            }

            //issue command
            issue_cmd(cmd);
        }
        private void issue_cmd(Cmd cmd)
        {
            MemAddr addr = cmd.addr;

            /*
             * if (cid == 0 && wb_mode) {
             *  Console.Write("@{0}\t", cycles - ts_start_wbmode);
             *  for (uint b = 0; b < addr.bid; b++) {
             *      Console.Write("{0,4}", "-");
             *  }
             *  Console.Write("{0,4}", cmd.type.ToString()[0]);
             *  for (uint b = addr.bid; b < bmax; b++) {
             *      Console.Write("{0,4}", "-");
             *  }
             *  Console.WriteLine();
             * }
             */

            List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];

            Dbg.Assert(cmd == cmd_q[0]);
            cmd_q.RemoveAt(0);
            BankStat bank_stat = Stat.banks2[addr.cid, addr.rid, addr.bid];
            BusStat  bus_stat  = Stat.busses2[addr.cid];

            //writeback mode stats
            if (wb_mode)
            {
                if (cmd.type == Cmd.TypeEnum.READ)
                {
                    rds_per_wb_mode++;
                }
                else if (cmd.type == Cmd.TypeEnum.WRITE)
                {
                    wbs_per_wb_mode++;
                }
            }

            //string dbg;
            switch (cmd.type)
            {
            case Cmd.TypeEnum.ACTIVATE:
                activate(addr);

                /*dbg = String.Format("@{0,6} DRAM ACTI: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
                //stats
                bank_stat.cmd_activate.Collect();
                bank_stat.utilization.Collect(timing.tRCD);

                //shadow row-buffer id
                shadow_rowid_per_procrankbank[cmd.pid, addr.rid, addr.bid] = addr.rowid;
                break;

            case Cmd.TypeEnum.PRECHARGE:
                precharge(addr);

                /*dbg = String.Format("@{0,6} DRAM PREC: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/
                //stats
                bank_stat.cmd_precharge.Collect();
                bank_stat.utilization.Collect(timing.tRP);
                break;

            case Cmd.TypeEnum.READ:
                read(addr);

                if (Config.proc.cache_insertion_policy == "PFA")
                {
                    Measurement.Dram_bus_conflict_reset(cmd.req.pid);
                }

                /*dbg = String.Format("@{0,6} DRAM READ: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/

                //writeback mode
                if (wb_mode && cmd.is_drain)
                {
                    Dbg.Assert(reads_to_drain > 0);
                    reads_to_drain--;
                }

                //stats
                bank_stat.cmd_read.Collect();
                bank_stat.utilization.Collect(timing.tCL);
                bus_stat.access.Collect();
                bus_stat.utilization.Collect(timing.tBL);
                break;

            case Cmd.TypeEnum.WRITE:
                write(addr);
                if (Config.proc.cache_insertion_policy == "PFA")
                {
                    Measurement.Dram_bus_conflict_reset(cmd.req.pid);
                }

                /*dbg = String.Format("@{0,6} DRAM WRTE: Channel {1}, Rank {2}, Bank {3}, Row {4}, Col {5}",
                 *  cycles, cid, addr.rid, addr.bid, addr.rowid, addr.colid);*/

                //writeback mode
                if (!wb_mode && cmd.is_drain)
                {
                    Dbg.Assert(writes_to_drain > 0);
                    writes_to_drain--;
                }
                else
                {
                    mwbmode.issued_write_cmd(cmd);
                }

                //stats
                bank_stat.cmd_write.Collect();
                bank_stat.utilization.Collect(timing.tCL);
                bus_stat.access.Collect();
                bus_stat.utilization.Collect(timing.tBL);
                break;

            default:
                //should never get here
                throw new System.Exception("DRAM: Invalid Cmd.");
            }
            //Debug.WriteLine(dbg);
        }
        private void issue_req(Req req)
        {
            //remove request from waiting queue
            List <Req> q = get_q(req);

            Dbg.Assert(q.Contains(req));
            q.Remove(req);

            //add to inflight queue
            MemAddr    addr       = req.addr;
            List <Req> inflight_q = inflightqs[addr.rid, addr.bid];

            Dbg.Assert(inflight_q.Count < inflight_q.Capacity);
            inflight_q.Add(req);

            //add to command queue
            List <Cmd> cmd_q = cmdqs[addr.rid, addr.bid];

            Dbg.Assert(cmd_q.Count == 0);
            List <Cmd> new_cmd_q = decode_req(req);

            Dbg.Assert(new_cmd_q.Count > 0);
            cmd_q.AddRange(new_cmd_q);

            Cmd cmd = cmd_q[0];

            //meta_mctrl
            meta_mctrl.issue_req(req);

            Dbg.Assert(cmd.req.addr.rowid == req.addr.rowid);

            //stats
            BankStat bstat = Stat.banks2[addr.cid, addr.rid, addr.bid];

            bstat.access.Collect();
            if (cmd.type == Cmd.TypeEnum.PRECHARGE || cmd.type == Cmd.TypeEnum.ACTIVATE)
            {
                //bank stat
                bstat.row_miss.Collect();
                bstat.row_miss_perproc[req.pid].Collect();

                //proc stat
                if (cmd.req.type == ReqType.RD)
                {
                    Stat.procs[req.pid].row_hit_rate_read.Collect(0);
                    Stat.procs[req.pid].row_miss_read.Collect();
                }
                else
                {
                    Stat.procs[req.pid].row_hit_rate_write.Collect(0);
                    Stat.procs[req.pid].row_miss_write.Collect();
                }


                req.hit = 2;

// Power Measurement:
                Sim.DRAM_power_statistics(req.pid, req.migrated_request, req.type, false);
//

                if (Config.proc.cache_insertion_policy == "PFA")
                {
//                      if ((!req.migrated_request) && (req.type == ReqType.RD))
                    Measurement.DramMissSetRowBufferChange(req);
                }
            }
            else
            {
                //bank stat
                bstat.row_hit.Collect();
                bstat.row_hit_perproc[req.pid].Collect();

                //proc stat
                if (cmd.req.type == ReqType.RD)
                {
                    Stat.procs[req.pid].row_hit_rate_read.Collect(1);
                    Stat.procs[req.pid].row_hit_read.Collect();
                }
                else
                {
                    Stat.procs[req.pid].row_hit_rate_write.Collect(1);
                    Stat.procs[req.pid].row_hit_write.Collect();
                }


                req.hit = 1;

// Power Measurement:
                Sim.DRAM_power_statistics(req.pid, req.migrated_request, req.type, true);
//

                if (Config.proc.cache_insertion_policy == "PFA")
                {
                    Measurement.DramHitSetRowBufferChange(req);
                }
            }

            if (Config.proc.cache_insertion_policy == "PFA")
            {
                Measurement.DramSetCorePrevRowid(req);
            }

            //issue command
            issue_cmd(cmd);

            if (cmd.addr != req.addr)
            {
                Console.Write("big error!");
            }
        }
Beispiel #7
0
        static Stat()
        {
            for (uint i = 0; i < procs.Length; i++)
                procs[i] = new ProcStat();
            for (uint i = 0; i < mctrls.Length; i++)
                mctrls[i] = new MemCtrlStat(i);
            for (uint i = 0; i < busses.Length; i++)
                busses[i] = new BusStat(i);

            for (uint c = 0; c < Config.mem.channel_max; c++) {
                scheds[c] = new MemSchedStat();
                for (uint r = 0; r < Config.mem.rank_max; r++) {
                    for (uint b = 0; b < 8; b++) {
                        banks[c, r, b] = new BankStat(c, r, b);
                    }
                }
            }
        }