private bool findBankIdx(mem_req req)
{
ulong s_row;
int mem_idx, ch_idx, rank_idx, bank_idx, row_idx;
MemoryRequest.mapAddr(req.address >> Config.cache_block, out s_row, out mem_idx, out ch_idx, out rank_idx, out bank_idx, out row_idx);
return(bank_idx == search_bank_idx);
}
/* HWA CODE */
// void _issueReq(int mshr, ulong addr, bool write, ulong reqTime )
void _issueReq(int mshr, ulong addr, bool write, ulong reqTime, int windowID)
/* HWA CODE END */
{
// Console.WriteLine("In _issueReq, before accessing the cache");
bool L1hit = false, L1upgr = false, L1ev = false, L1wb = false;
bool L2access = false, L2hit = false, L2ev = false, L2wb = false, c2c = false;
Simulator.network.cache.access(m_ID, addr, write,
delegate() { reqDone(addr, mshr, write); },
out L1hit, out L1upgr, out L1ev, out L1wb, out L2access, out L2hit, out L2ev, out L2wb, out c2c);
if ((m_ID == 0) && (addr == 0))
{
Console.WriteLine("cacheAccess l1_hit:{0},l2_acc:{1},l2_hit:{2}", L1hit, L2access, L2hit);
}
// TODO: buggy code -> causes exception with dup key in the hash table
/*if (L2access && L2hit)
* {
* for (int i = 0; i < m_mshrs.Length; i++)
* {
* if (m_mshrs[i].valid && i != mshr)
* {
* if (m_mshrs[i].reqTime < reqTime)
* {
* Simulator.stats.L2_potential_MLP[m_ID].Add();
* break;
* }
* }
* }
* }*/
// Console.WriteLine("In _issueReq:after accessing the cache");
if (!L1hit)
{
Simulator.network._cycle_L1_misses++;
Simulator.controller.L1misses[m_ID]++;
Simulator.stats.L1misses[m_ID].Add();
}
if (m_stats_active)
{
Simulator.stats.L1_accesses_persrc[m_ID].Add();
if (L1hit)
{
Simulator.stats.L1_hits_persrc[m_ID].Add();
}
else
{
Simulator.stats.L1_misses_persrc[m_ID].Add();
Simulator.stats.L1_misses_persrc_period[m_ID].Add();
}
if (L1upgr)
{
Simulator.stats.L1_upgr_persrc[m_ID].Add();
}
if (L1ev)
{
Simulator.stats.L1_evicts_persrc[m_ID].Add();
}
if (L1wb)
{
Simulator.stats.L1_writebacks_persrc[m_ID].Add();
}
if (c2c)
{
Simulator.stats.L1_c2c_persrc[m_ID].Add();
}
if (L2access)
{
Simulator.stats.L2_accesses_persrc[m_ID].Add();
if (L2hit)
{
Simulator.stats.L2_hits_persrc[m_ID].Add();
}
else
{
Simulator.stats.L2_misses_persrc[m_ID].Add();
}
if (L2ev)
{
Simulator.stats.L2_evicts_persrc[m_ID].Add();
}
if (L2wb)
{
Simulator.stats.L2_writebacks_persrc[m_ID].Add();
}
}
/* HWA CODE */
if ((L2access && !L2hit && !write) || (m_is_HWA && !write))
{
m_ins.setDramReq(windowID);
}
if (preCheck_num == 0)
{
ulong s_row;
int mem_idx, ch_idx, rank_idx, bank_idx, row_idx;
// MemoryRequest.mapAddr(addr>>Config.cache_block, out s_row, out mem_idx, out ch_idx, out rank_idx, out bank_idx, out row_idx );
MemoryRequest.mapAddr(ID, addr >> Config.cache_block, out s_row, out mem_idx, out ch_idx, out rank_idx, out bank_idx, out row_idx);
Simulator.QoSCtrl.issue_request(m_ID, mem_idx, ch_idx, false);
}
else
{
preCheck_num--;
}
/* HWA CODE END */
}
}
