public void set(int pid, ReqType type, ReqType proc_req_type, ulong paddr)
{
//state
this.pid = pid;
this.type = type;
this.proc_req_type = proc_req_type;
this.row_hit = true;
this.actual_addr = paddr;
//address
if (Config.mctrl.page_randomize) {
this.paddr = prand.get_paddr(paddr);
}
else if (Config.mctrl.page_sequence){
this.paddr = pseq.get_paddr(paddr);
}
else {
this.paddr = paddr;
}
this.block_addr = this.paddr >> Config.proc.block_size_bits;
this.addr = MemMap.translate(this.paddr, pid);
//misc
this.reset();
}
/// <summary>
/// Constructor that defines the requirements for a Building.
/// </summary>
/// <param name="unitReqs">List of UnitStats of Units needed.</param>
/// <param name="buildingReqs">List of BuildingStats of Buildings needed.</param>
/// <param name="bstats">BuildingStats of the kind of Building the requirements are being defined for.</param>
public ReqList(List<UnitStats> unitReqs, List<BuildingStats> buildingReqs, BuildingStats bstats)
{
this.unitReqs = unitReqs;
this.buildingReqs = buildingReqs;
this.bstats = bstats;
type = ReqType.Building;
}
public int has_addr_sampled_set(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
if (valid[set_index, i] == true && cache[set_index, i] == block_addr && set_index % Config.proc.sample == 0)
{
return(i + 1000);
}
}
if (set_index % Config.proc.sample == 0)
{
return(1000);
}
else
{
return(100000);
}
}
/// <summary>
/// Constructor that defines the requirements for a Unit.
/// </summary>
/// <param name="unitReqs">List of UnitStats of Units needed.</param>
/// <param name="buildingReqs">List of BuildingStats of Buildings needed</param>
/// <param name="ustats">UnitStats of the kind of Unit the requirements are being defined for.</param>
public ReqList(List <UnitStats> unitReqs, List <BuildingStats> buildingReqs, UnitStats ustats)
{
this.unitReqs = unitReqs;
this.buildingReqs = buildingReqs;
this.ustats = ustats;
type = ReqType.Unit;
}
/**
* Searches for a block within the cache.
* If found, sets the dirty bit.
*
* @param block_addr block address
* @param inst_type instruction type
* @return if found, true; otherwise, false
*/
public bool has_addr(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++) {
if (cache[set_index, i] == block_addr) {
//hit
hit++;
timestamp[set_index, i] = cycle;
if (inst_type == ReqType.WR)
{
dirty[set_index, i] = true;
}
return true;
}
}
//couldn't find block_addr; miss
miss++;
return false;
}
new public bool is_q_full(int pid, ReqType rw, uint rid, uint bid)
{
/* read queue */
if (rw == ReqType.RD)
{
//yang modified:
int temp = 0;
for (int i = 0; i < rmax; i++)
{
for (int j = 0; j < bmax; j++)
{
List <Req> q = readqs[i, j];
temp = temp + q.Count;
}
}
// return q.Count == q.Capacity;
return(temp >= readqs[0, 0].Capacity);
}
/* write queue */
if (mctrl_writeq.Count >= mctrl_writeq.Capacity)
{
return(true);
}
//writeback throttle
bool is_throttle = wbthrottle.is_throttle(pid);
return(is_throttle);
}
private void get_req_cache_unfiltered(ref int cpu_inst_cnt, ref string line, Char[] delim, ref string[] tokens, out Req rd_req, out Req wb_req)
{
Dbg.AssertPrint(tokens.Length == 6, "trace line = " + line);
ReqType req_type = (int.Parse(tokens[5]) == 0) ? ReqType.READ : ReqType.WRITE;
// Read-only requests
while (Config.proc.wb == false && req_type == ReqType.WRITE)
{
line = read_trace();
tokens = line.Split(delim);
req_type = (int.Parse(tokens[5]) == 0) ? ReqType.READ : ReqType.WRITE;
}
// Set instruction count b/w requests
ulong icount = ulong.Parse(tokens[0]);
if (cur_inst_count == 0)
{
cpu_inst_cnt = 0;
}
else
{
cpu_inst_cnt = (int)(icount - cur_inst_count);
Dbg.AssertPrint(cpu_inst_cnt >= 0, "Negative instruction count");
}
cur_inst_count = icount;
// Parse virtual address
ulong vaddr = ulong.Parse(tokens[2]);
vaddr = vaddr + (((ulong)pid) << 48);
rd_req = RequestPool.Depool();
rd_req.Set(pid, req_type, vaddr);
wb_req = null;
}
public void set(int pid, ReqType type, ulong paddr)
{
//state
this.pid = pid;
this.type = type;
//address
if (Config.mctrl.page_randomize)
{
this.paddr = prand.get_paddr(paddr);
}
else if (Config.mctrl.page_sequence)
{
this.paddr = pseq.get_paddr(paddr);
}
// else if (Config.mctrl.remapping) {
// if (mapping_table.contains(paddr >> PAGE_SIZE)) {
// this.paddr = mapping_table[paddr >> PAGE_SIZE];
// }
// }
else
{
this.paddr = paddr;
}
this.block_addr = this.paddr >> Config.proc.block_size_bits;
this.addr = MemMap.translate(this.paddr, pid);
//misc
this.reset();
}
/// <summary>
/// Constructor that defines the requirements for a Unit.
/// </summary>
/// <param name="unitReqs">List of UnitStats of Units needed.</param>
/// <param name="buildingReqs">List of BuildingStats of Buildings needed</param>
/// <param name="ustats">UnitStats of the kind of Unit the requirements are being defined for.</param>
public ReqList(List<UnitStats> unitReqs, List<BuildingStats> buildingReqs, UnitStats ustats)
{
this.unitReqs = unitReqs;
this.buildingReqs = buildingReqs;
this.ustats = ustats;
type = ReqType.Unit;
}
public void set(int pid, ReqType type, ReqType proc_req_type, ulong paddr)
{
//state
this.pid = pid;
this.type = type;
this.proc_req_type = proc_req_type;
this.row_hit = true;
this.actual_addr = paddr;
//address
if (Config.mctrl.page_randomize)
{
this.paddr = prand.get_paddr(paddr);
}
else if (Config.mctrl.page_sequence)
{
this.paddr = pseq.get_paddr(paddr);
}
else
{
this.paddr = paddr;
}
this.block_addr = this.paddr >> Config.proc.block_size_bits;
this.addr = MemMap.translate(this.paddr);
this.is_prefetch = false;
//misc
this.reset();
}
/**
* Searches for a block within the cache.
* If found, sets the dirty bit.
*
* @param block_addr block address
* @param inst_type instruction type
* @return if found, true; otherwise, false
*/
public bool has_addr(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.l1_cache_assoc; i++)
{
if (cache[set_index, i] == block_addr)
{
//hit
hit++;
timestamp[set_index, i] = cycle;
if (inst_type == ReqType.WR)
{
dirty[set_index, i] = true;
}
return(true);
}
}
//couldn't find block_addr; miss
miss++;
return(false);
}
public ulong cache_add(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
int set_index = (int)(block_addr % set_max);
//empty entry within a set
int empty_entry_index = -1;
//lru entry within a set
int lru_entry_index = -1;
ulong lru_timestamp = ulong.MaxValue;
//search for empty or lru entry
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
//make sure not already in cache
Debug.Assert(cache[set_index, i] != block_addr);
if (cache[set_index, i] == Proc.NULL_ADDRESS)
{
//found empty entry
empty_entry_index = i;
break;
}
if (timestamp[set_index, i] < lru_timestamp)
{
lru_timestamp = timestamp[set_index, i];
lru_entry_index = i;
}
}
ulong return_addr = Proc.NULL_ADDRESS;
//populate empty entry
if (empty_entry_index != -1)
{
cache[set_index, empty_entry_index] = block_addr;
timestamp[set_index, empty_entry_index] = cycle;
dirty[set_index, empty_entry_index] = (inst_type == ReqType.WR);
return(return_addr);
}
//replace lru entry
if (dirty[set_index, lru_entry_index])
{
return_addr = cache[set_index, lru_entry_index];
}
cache[set_index, lru_entry_index] = block_addr;
timestamp[set_index, lru_entry_index] = cycle;
dirty[set_index, lru_entry_index] = (inst_type == ReqType.WR);
return(return_addr);
}
/**
* Add block to the cache.
* Either an empty or the LRU block is populated.
* @param block_addr block address
* @param inst_type instruction type
* @return if LRU block is populated, its tag; if empty block is populated, 0
*/
public ulong cache_add(ulong block_addr, ReqType inst_type, ulong pid)
{
//progress time
cycle++;
//calculate set index
int set_index = (int)(block_addr % set_max);
//empty entry within a set
int empty_entry_index = -1;
//lru entry within a set
int lru_entry_index = -1;
ulong lru_timestamp = ulong.MaxValue;
//search for empty or lru entry
for (int i = 0; i < Config.proc.l1_cache_assoc; i++)
{
//make sure not already in cache
Debug.Assert(cache[set_index, i] != block_addr);
if (cache[set_index, i] == Proc.NULL_ADDRESS) {
//found empty entry
empty_entry_index = i;
break;
}
if (timestamp[set_index, i] < lru_timestamp) {
lru_timestamp = timestamp[set_index, i];
lru_entry_index = i;
}
}
ulong return_addr = Proc.NULL_ADDRESS;
//populate empty entry
if (empty_entry_index != -1) {
cache[set_index, empty_entry_index] = block_addr;
timestamp[set_index, empty_entry_index] = cycle;
dirty[set_index, empty_entry_index] = (inst_type == ReqType.WR);
core_id[set_index, empty_entry_index] = pid;
return return_addr;
}
//replace lru entry
if (dirty[set_index, lru_entry_index])
return_addr = cache[set_index, lru_entry_index];
cache[set_index, lru_entry_index] = block_addr;
timestamp[set_index, lru_entry_index] = cycle;
dirty[set_index, lru_entry_index] = (inst_type == ReqType.WR);
core_id[set_index, lru_entry_index] = pid;
if (Config.fst)
{
if (Sim.procs[pid].pollution_vector.check_filter(block_addr)) Sim.procs[pid].pollution_vector.clear_pollution_vector(block_addr);
}
return return_addr;
}
private static Cmd masa_cmd_issue(ReqType r, MemAddr a, Cmd cmd, NodeMachine bank, NodeMachine subarray)
{
var open_said = bank.OpenChildrenId;
// subarray-miss
if (!open_said.Contains(a.said))
{
cmd.Type = CmdType.ACT;
return(cmd);
}
// row-miss
if (!subarray.OpenChildrenId.Contains(a.rowid))
{
cmd.Type = CmdType.PRE_SA;
return(cmd);
}
// not the most-recently-opened subarray
if (open_said[0] != a.said && !Config.mctrl.b_piggyback_SEL_SA)
{
cmd.Type = CmdType.SEL_SA;
return(cmd);
}
// row-hit
cmd.Type = r == ReqType.READ ? CmdType.RD : CmdType.WR;
return(cmd);
}
/// <summary>
/// Constructor that defines the requirements for a Building.
/// </summary>
/// <param name="unitReqs">List of UnitStats of Units needed.</param>
/// <param name="buildingReqs">List of BuildingStats of Buildings needed.</param>
/// <param name="bstats">BuildingStats of the kind of Building the requirements are being defined for.</param>
public ReqList(List <UnitStats> unitReqs, List <BuildingStats> buildingReqs, BuildingStats bstats)
{
this.unitReqs = unitReqs;
this.buildingReqs = buildingReqs;
this.bstats = bstats;
type = ReqType.Building;
}
private static Cmd salp2_cmd_issue(ReqType r, MemAddr a, Cmd cmd, NodeMachine bank, NodeMachine subarray)
{
Dbg.Assert(bank.OpenChildrenId.Count <= 2);
// closed bank
if (bank.OpenChildrenId.Count == 0)
{
cmd.Type = CmdType.ACT;
return(cmd);
}
// open bank (one subarray)
if (bank.OpenChildrenId.Count == 1)
{
// subarray-miss
if (bank.OpenChildrenId[0] != a.said)
{
cmd.Type = CmdType.ACT;
return(cmd);
}
// row-miss
if (subarray.OpenChildrenId[0] != a.rowid)
{
cmd.Type = CmdType.PRE_SA;
return(cmd);
}
// row-hit
cmd.Type = r == ReqType.READ ? CmdType.RD : CmdType.WR;
return(cmd);
}
// open bank (two subarrays)
// all subarray-miss
if (!bank.OpenChildrenId.Contains(a.said))
{
cmd.Type = CmdType.PRE_SA;
cmd.Addr.said = (uint)bank.OpenChildrenId[1]; // close least-recently-opened subarray
return(cmd);
}
// not the most-recently-opened subarray
if (bank.OpenChildrenId[0] != a.said)
{
cmd.Type = CmdType.PRE_SA;
cmd.Addr.said = (uint)bank.OpenChildrenId[1]; // close least-recently-opened subarray
return(cmd);
}
// row-miss
if (subarray.OpenChildrenId[0] != a.rowid)
{
cmd.Type = CmdType.PRE_SA;
return(cmd);
}
// row-hit
cmd.Type = r == ReqType.READ ? CmdType.RD : CmdType.WR;
return(cmd);
}
public ActionResult manageReqType(managementVM management, int?ReqTypeID, string Search)
{
if (ModelState.IsValid)
{
if (management.ReqType != null)
{
var reqtype = new ReqType
{
ReqType1 = management.ReqType.ReqType1
};
db.ReqType.Add(reqtype);
db.SaveChanges();
LoadReqType();
return(RedirectToAction("manageReqType"));
}
else if (ReqTypeID != null)
{
var mydeletetype = db.ReqType.Find(ReqTypeID);
db.ReqType.Remove(mydeletetype);
db.SaveChanges();
LoadReqType();
return(RedirectToAction("manageReqType"));
}
else if (Search != null || Search != "")
{
string FN = string.Empty;
string LN = string.Empty;
string[] m = Search.Split(null);//if the splitting char is null it is assume that the delimiter is a whie space
var mymanagement = new managementVM();
if (m.Length > 1)
{
FN = m[0];
LN = m[1];
mymanagement.Tenants = db.Tenant.Where(c => c.FirstName.Contains(Search) || c.LastName.Contains(Search) || c.FirstName.Contains(FN) && c.LastName.Contains(LN))
.Select(c => new TenantVM {
ID = c.ID, FirstName = c.FirstName, LastName = c.LastName, aptID = (int)c.aptID, Phone = c.Phone, created = c.Created
}).ToList();
}
else
{
mymanagement.Tenants = db.Tenant.Where(c => c.FirstName.Contains(Search) || c.LastName.Contains(Search))
.Select(c => new TenantVM {
ID = c.ID, FirstName = c.FirstName, LastName = c.LastName, aptID = (int)c.aptID, Phone = c.Phone, created = c.Created
}).ToList();
}
LoadReqType();
return(View(mymanagement));
}
}
return(View());
}
/// <summary>
/// Constructor, builds a ReqList defined by the XMl string for a Unit defined by the UnitStats.
/// </summary>
/// <param name="xml"></param>
/// <param name="ustats"></param>
public ReqList(string xml, UnitStats ustats)
{
this.unitReqs = new List<UnitStats>();
this.buildingReqs = new List<BuildingStats>();
this.ustats = ustats;
type = ReqType.Unit;
readReqXML(xml);
}
/// <summary>
/// Contructor. Given an xml string and a BuildingStats object, this constructor will create a ReqList object for the
/// Building defined by bstats based on the requirements described in the xml string.
/// </summary>
/// <param name="xml"></param>
/// <param name="bstats"></param>
public ReqList(string xml, BuildingStats bstats)
{
this.unitReqs = new List <UnitStats>();
this.buildingReqs = new List <BuildingStats>();
this.bstats = bstats;
type = ReqType.Building;
readReqXML(xml);
}
public static void NVM_power_statistics(int p, bool migration, ReqType type, bool hit)
{
if (processor_finished[p])
{
return;
}
if (migration)
{
if (type == ReqType.RD)
{
if (hit)
{
NVM_migration_read_hit[p] = NVM_migration_read_hit[p] + 1;
}
else
{
NVM_migration_read_miss[p] = NVM_migration_read_miss[p] + 1;
}
}
else
{
if (hit)
{
NVM_migration_write_hit[p] = NVM_migration_write_hit[p] + 1;
}
else
{
NVM_migration_write_miss[p] = NVM_migration_write_miss[p] + 1;
}
}
}
else
{
if (type == ReqType.RD)
{
if (hit)
{
NVM_processor_read_hit[p] = NVM_processor_read_hit[p] + 1;
}
else
{
NVM_processor_read_miss[p] = NVM_processor_read_miss[p] + 1;
}
}
else
{
if (hit)
{
NVM_processor_write_hit[p] = NVM_processor_write_hit[p] + 1;
}
else
{
NVM_processor_write_miss[p] = NVM_processor_write_miss[p] + 1;
}
}
}
}
public void AddReq(BasicRequire req, ReqType type)
{
_reqListArr[(int)type].Add(req);
try
{
_workSem.Release();
}catch (Exception e)
{
}
}
/**
* Add block to the cache.
* Either an empty or the LRU block is populated.
* @param block_addr block address
* @param inst_type instruction type
* @return if LRU block is populated, its tag; if empty block is populated, 0
*/
public virtual ulong cache_add(ulong block_addr, ReqType inst_type, int pid)
{
if (IsVoid)
return Proc.NULL_ADDRESS;
//calculate set index
int setIndex = (int)(block_addr % SetMax);
//empty entry within a set
int emptyEntryIndex = -1;
//lru entry within a set
int lruEntryIndex = -1;
//search for empty or lru entry
for (int i = 0; i < Assoc; i++)
{
//make sure not already in cache
Dbg.Assert(cache[setIndex, i] != block_addr);
if (cache[setIndex, i] == Proc.NULL_ADDRESS)
{
emptyEntryIndex = i;
break;
}
}
// Replace LRU
if (emptyEntryIndex == -1)
{
lruEntryIndex = LruChainList[setIndex].Last.Value;
UpdateLRU(setIndex, lruEntryIndex);
}
else
LruChainList[setIndex].AddFirst(emptyEntryIndex);
ulong return_addr = Proc.NULL_ADDRESS;
int replaceAssocIdx = (emptyEntryIndex != -1) ?
emptyEntryIndex : lruEntryIndex;
// Check if the replacement is non-empty and dirty
if ((replaceAssocIdx == lruEntryIndex) && Dirty[setIndex, lruEntryIndex])
{
return_addr = cache[setIndex, lruEntryIndex];
if (!IsL2C)
Stat.procs[CachePid].l1c_dirty_eviction.collect();
else
Stat.caches[CachePid == -1 ? 0 : CachePid].l2c_dirty_eviction.collect();
}
// Add the new block
cache[setIndex, replaceAssocIdx] = block_addr;
Dirty[setIndex, replaceAssocIdx] = (inst_type == ReqType.WRITE);
CoreId[setIndex, replaceAssocIdx] = pid; // for partitioning
return return_addr;
}
private static string execute(ReqType reqType, string user, Phone device, Host host)
{
var client = new RestClient("http://" + host.IP + ":8080/emservice/EMServiceServlet");
var request = new RestRequest(Method.POST);
request.AddParameter(_encodeType, encodeReq(reqType, user, device, host),
ParameterType.RequestBody);
IRestResponse response = client.Execute(request);
return(response.Content);
}
public override ulong cache_add(ulong block_addr, ReqType inst_type, int pid)
{
if (Config.mctrl.villa_lru)
{
return(base.cache_add(block_addr, inst_type, pid));
}
//calculate set index
int setIndex = (int)(block_addr % SetMax);
//empty entry within a set
int emptyEntryIndex = -1;
//lru entry within a set
int lruEntryIndex = -1;
//search for empty or lru entry
for (int i = 0; i < Assoc; i++)
{
//make sure not already in cache
Dbg.Assert(cache[setIndex, i] != block_addr);
if (cache[setIndex, i] == Proc.Proc.NULL_ADDRESS)
{
emptyEntryIndex = i;
break;
}
}
// Replace least benefit
if (emptyEntryIndex == -1)
{
lruEntryIndex = BBCCounter.IndexOf(BBCCounter.Min());
BBCCounter[lruEntryIndex] = 0;
// Halve benefit
for (int i = 0; i < Assoc; i++)
{
BBCCounter[i] /= 2;
}
}
else
{
BBCCounter[emptyEntryIndex]++;
}
ulong returnAddr = Proc.Proc.NULL_ADDRESS;
int replaceAssocIdx = (emptyEntryIndex != -1) ?
emptyEntryIndex : lruEntryIndex;
// Add the new block
cache[setIndex, replaceAssocIdx] = block_addr;
Dirty[setIndex, replaceAssocIdx] = (inst_type == ReqType.WRITE);
CoreId[setIndex, replaceAssocIdx] = pid; // for partitioning
return(returnAddr);
}
/**
* Add block to the cache.
* Either an empty or the LRU block is populated.
* @param block_addr block address
* @param inst_type instruction type
* @return if LRU block is populated, its tag; if empty block is populated, 0
*/
public ulong cache_add(ulong block_addr, ReqType inst_type, ulong pid)
{
cycle++;
//calculate set index
int set_index = (int)(block_addr % set_max);
//empty entry within a set
int empty_entry_index = -1;
//lru entry within a set
int lru_entry_index = -1;
ulong lru_timestamp = ulong.MaxValue;
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
//make sure not already in cache
Debug.Assert(cache[set_index, i] != block_addr);
if (cache[set_index, i] == Proc.NULL_ADDRESS) {
//found empty entry
empty_entry_index = i;
break;
}
if (timestamp[set_index, i] < lru_timestamp) {
lru_timestamp = timestamp[set_index, i];
lru_entry_index = i;
}
}
ulong return_addr = Proc.NULL_ADDRESS;
//populate empty entry
if (empty_entry_index != -1) {
cache[set_index, empty_entry_index] = block_addr;
timestamp[set_index, empty_entry_index] = cycle;
dirty[set_index, empty_entry_index] = (inst_type == ReqType.WR);
core_id[set_index, empty_entry_index] = pid;
return return_addr;
}
if (dirty[set_index, lru_entry_index])
return_addr = cache[set_index, lru_entry_index];
cache[set_index, lru_entry_index] = block_addr;
timestamp[set_index, lru_entry_index] = cycle;
dirty[set_index, lru_entry_index] = (inst_type == ReqType.WR);
core_id[set_index, lru_entry_index] = pid;
return return_addr;
}
public override void CacheStats(ReqType req_type, bool hit, ulong block_addr = 0)
{
if (!hit)
{
Stat.banks[_cid, _rid, _bid].villa_hit_rate.collect(0);
Stat.banks[_cid, _rid, _bid].villa_misses.collect();
}
else
{
Stat.banks[_cid, _rid, _bid].villa_hit_rate.collect(1);
Stat.banks[_cid, _rid, _bid].villa_hits.collect();
}
}
public Request(string req)
{
_req = req;
// 要求URL確認 ＆ 応答内容生成
switch (req.Split(' ')[0])
{
case "GET":
_type = ReqType.GET;
MatchCollection get_reg = Regex.Matches(req, @"GET (?<path>/[a-zA-Z0-9/]*.(html|txt|css|js|jpeg|jpg|png|pdf|xml|gif))", RegexOptions.IgnoreCase | RegexOptions.Singleline);
foreach (Match m in get_reg)
{
string path = Environment.CurrentDirectory + @"\Html\" + m.Groups["path"].ToString().Replace('/', '\\');
bodys = new Dictionary<string, string>();
bodys.Add("path", path);
}
break;
case "POST":
bodys = new Dictionary<string, string>();
_type = ReqType.POST;
//MatchCollection post_reg = Regex.Matches(req, @"POST /(?<cmd>[a-zA-Z0-9]*) ", RegexOptions.IgnoreCase | RegexOptions.Singleline);
// bodysにidやvalueを格納する
bodys = new Dictionary<string, string>();
// playerid
var reg_player = new Regex(@"playerid=(?<id>[0-9a-zA-Z]*)", RegexOptions.IgnoreCase | RegexOptions.Singleline);
var player = reg_player.Match(req);
bodys.Add("playerid", player.Groups["id"].ToString());
// probid
var reg_prob = new Regex(@"problemid=(?<id>[0-9a-zA-Z]*)", RegexOptions.IgnoreCase | RegexOptions.Singleline);
var prob = reg_prob.Match(req);
bodys.Add("probid", prob.Groups["id"].ToString());
// language : c, c++, java, c#, vb (1, 2, 3, 4, 5)
var reg_lang = new Regex(@"language=(?<id>[0-9]*)", RegexOptions.IgnoreCase | RegexOptions.Singleline);
var lang = reg_lang.Match(req);
bodys.Add("lang", lang.Groups["id"].ToString());
// answer
bodys.Add("answer", req.Substring(req.IndexOf("answer=") + "answer=".Length));
break;
}
}
public override async Task SendRequest(ReqType reqType, uint seq, byte[] plBuff, int offset, int len)
{
try
{
if (len > config.CMD_MAX_PLSZ)
{
throw new ArgumentException("len > CMD_MAX_PLSZ", nameof(len));
}
//write sequence number
int pos = config.CMD_HDR_SIZE;
int seqLen = 0;
if (seq > 0)
{
if (config.CMD_SEQ_SIZE == 4)
{
sendBuff[pos++] = (byte)(seq & 0xFF);
sendBuff[pos++] = (byte)((seq >> 8) & 0xFF);
sendBuff[pos++] = (byte)((seq >> 16) & 0xFF);
sendBuff[pos++] = (byte)((seq >> 24) & 0xFF);
}
else
{
throw new Exception("config.CMD_SEQ_SIZE != 4");
}
seqLen = config.CMD_SEQ_SIZE;
}
else
{
len = 0;
}
//write payload
Buffer.BlockCopy(plBuff, offset, sendBuff, pos, len);
pos += len;
sendBuff[0] = (byte)((int)reqType | (len + seqLen + config.CMD_CRC_SIZE));
//write crc
int testLen = len + seqLen + config.CMD_HDR_SIZE;
sendBuff[testLen] = CRC8.Calculate(sendBuff, 0, testLen);
//send data
using (var cts = new CancellationTokenSource())
{
cts.CancelAfter(UseCommitTimeout?config.COMMIT_TIMEOUT:config.CMD_TIMEOUT);
await link.WriteAsync(sendBuff, 0, testLen + config.CMD_CRC_SIZE, cts.Token);
}
}
catch (TaskCanceledException ex)
{
throw new TimeoutException("SendRequest was timed out", ex);
}
}
/**
* Searches for a block within the cache.
* If found, sets the dirty bit.
*
* @param block_addr block address
* @param inst_type instruction type
* @return if found, true; otherwise, false
*/
public bool has_addr(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
if (valid[set_index, i] == true && cache[set_index, i] == block_addr)
{
//hit
hit++;
if (inst_type == ReqType.WR)
{
dirty[set_index, i] = true;
}
ulong temp_cache = cache[set_index, i];
bool temp_dirty = dirty[set_index, i];
ulong temp_core_id = core_id[set_index, i];
bool temp_valid = valid[set_index, i];
for (int j = i; j < Config.proc.cache_assoc - 1; j++)
{
cache[set_index, j] = cache[set_index, j + 1];
dirty[set_index, j] = dirty[set_index, j + 1];
core_id[set_index, j] = core_id[set_index, j + 1];
valid[set_index, j] = valid[set_index, j + 1];
}
cache[set_index, Config.proc.cache_assoc - 1] = temp_cache;
dirty[set_index, Config.proc.cache_assoc - 1] = temp_dirty;
core_id[set_index, Config.proc.cache_assoc - 1] = temp_core_id;
valid[set_index, Config.proc.cache_assoc - 1] = temp_valid;
return(true);
}
}
miss++;
return(false);
}
/// <summary>
/// Generates hash code
/// </summary>
/// <returns>hash code</returns>
public override int GetHashCode()
{
var hashCode = 2126638501;
hashCode = hashCode * -1521134295 + EqualityComparer <string> .Default.GetHashCode(ReqName);
hashCode = hashCode * -1521134295 + ReqType.GetHashCode();
hashCode = hashCode * -1521134295 + DocEntry.GetHashCode();
hashCode = hashCode * -1521134295 + DocNum.GetHashCode();
hashCode = hashCode * -1521134295 + DocDate.GetHashCode();
hashCode = hashCode * -1521134295 + DocDueDate.GetHashCode();
hashCode = hashCode * -1521134295 + TaxDate.GetHashCode();
hashCode = hashCode * -1521134295 + ReqDate.GetHashCode();
hashCode = hashCode * -1521134295 + EqualityComparer <List <PRQ1> > .Default.GetHashCode(Items);
return(hashCode);
}
public void set_prefetch(int pid, ReqType type, ReqType proc_req_type, ulong paddr)
{
//state
this.pid = pid;
this.type = type;
this.proc_req_type = proc_req_type;
this.row_hit = true;
this.actual_addr = paddr;
this.paddr = paddr;
//address
this.block_addr = this.paddr >> Config.proc.block_size_bits;
this.addr = MemMap.translate(this.paddr);
this.is_prefetch = true;
//misc
this.reset();
}
public void set(int pid, ReqType type, ulong paddr, bool flag)
{
if (flag == false)
{
Console.Write("Mistakenly call request set\n");
}
//state
this.pid = pid;
this.type = type;
this.paddr = paddr;
this.block_addr = this.paddr >> Config.proc.block_size_bits;
this.addr = MemMap.translate(this.paddr, pid);
//misc
this.reset();
}
public static async Task <HttpResponseMessage> ReqRest(string url, ReqType reqType, HttpContent content = null)
{
HttpClient clientRest = new HttpClient();
HttpResponseMessage response = null;
switch (reqType)
{
case ReqType.GET: response = await clientRest.GetAsync(url); break;
case ReqType.POST: response = await clientRest.PostAsync(url, content); break;
case ReqType.PUT: response = await clientRest.PutAsync(url, content); break;
case ReqType.DELETE: response = await clientRest.DeleteAsync(url); break;
}
response.EnsureSuccessStatusCode();
return(response);
}
public void Reset()
{
Pid = -1;
Type = ReqType.READ;
CacheHit = false;
TracePaddr = 0;
Paddr = 0;
BlockAddr = 0;
Addr.Reset();
TsArrival = -1;
TsDeparture = -1;
Latency = -1;
WbReq = null;
Callback = null;
RequiredActivate = false;
Marked = false;
RdWr = false;
DirtyInsert = false;
CpyGenReq = false;
}
public bool cache_remove(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.l1_cache_assoc; i++)
{
if (cache[set_index, i] == block_addr)
{
cache[set_index, i] = Proc.NULL_ADDRESS;
return(true);
}
}
return(false);
}
public bool is_q_full(int pid, ReqType rw, uint rid, uint bid)
{
/* read queue */
if (rw == ReqType.RD)
{
List <Req> q = readqs[rid, bid];
return(q.Count == q.Capacity);
}
/* write queue */
if (mctrl_writeq.Count == mctrl_writeq.Capacity)
{
return(true);
}
//writeback throttle
bool is_throttle = wbthrottle.is_throttle(pid);
return(is_throttle);
}
public int has_addr_sampled_set(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
if (set_index % Config.proc.sample == 0)
{
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
recency_position[i] = 0;
for (int j = 0; j < Config.proc.cache_assoc; j++)
{
if (timestamp[set_index, i] >= timestamp[set_index, j] && i != j)
{
recency_position[i]++;
}
}
}
}
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
if (cache[set_index, i] == block_addr && set_index % Config.proc.sample == 0)
{
return(recency_position[i] + 1000);
}
}
if (set_index % Config.proc.sample == 0)
{
return(1000);
}
else
{
return(100000);
}
//couldn't find block_addr; miss
}
public void Set(int pid, ReqType type, ulong paddr)
{
// state
Pid = pid;
Type = type;
// address
TracePaddr = paddr;
if (Config.mctrl.page_randomize)
{
Paddr = Prand.get_paddr(paddr);
}
else if (Config.mctrl.page_sequence)
{
Paddr = Pseq.get_paddr(paddr);
}
else if (Config.mctrl.page_contiguous)
{
Paddr = Pcontig.get_paddr(paddr);
}
else
{
Paddr = paddr;
}
BlockAddr = Paddr >> Config.proc.block_size_bits;
Addr = MemMap.Translate(Paddr);
Stat.procs[pid].allocated_physical_pages.collect();
reset_timing();
// Word offset
ulong pwo = (Paddr & (63)) >> 2;
Dbg.AssertPrint(pwo == ((paddr & (63)) >> 2),
"Word offset should be the same for both virtual and physical addresses.");
Dbg.AssertPrint(pwo < 16, "There should be only 8 words in a cacheline=" + pwo);
WordOffset = (int)pwo;
}
public ulong cache_add(ulong block_addr, ReqType inst_type)
{
// Console.Write(" Cache number " + cache_count + "\n");
//progress time
cycle++;
//calculate set index
int set_index = (int)(block_addr % set_max);
//empty entry within a set
int empty_entry_index = -1;
//lru entry within a set
int lru_entry_index = -1;
ulong lru_timestamp = ulong.MaxValue;
//search for empty or lru entry
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
//make sure not already in cache
Debug.Assert(cache[set_index, i] != block_addr);
if (cache[set_index, i] == Proc.NULL_ADDRESS) {
//found empty entry
empty_entry_index = i;
break;
}
if (timestamp[set_index, i] < lru_timestamp) {
lru_timestamp = timestamp[set_index, i];
lru_entry_index = i;
}
}
ulong return_addr = Proc.NULL_ADDRESS;
//populate empty entry
if (empty_entry_index != -1) {
cache[set_index, empty_entry_index] = block_addr;
timestamp[set_index, empty_entry_index] = cycle;
dirty[set_index, empty_entry_index] = (inst_type == ReqType.WR);
return return_addr;
}
// Console.Write(" Cache " + cache_count + " Replacing\n");
//replace lru entry
if (dirty[set_index, lru_entry_index])
return_addr = cache[set_index, lru_entry_index];
cache[set_index, lru_entry_index] = block_addr;
timestamp[set_index, lru_entry_index] = cycle;
dirty[set_index, lru_entry_index] = (inst_type == ReqType.WR);
return return_addr;
}
private byte[] ProcessExpression(ReqType type, string expression)
{
if (!IsInDebugMode(_applicationObject)) {
return FormatMessage(RespType.Error, "Not in debug mode");
}
Expression expr = null;
try {
expr = _applicationObject.Debugger.GetExpression(expression);
} catch (System.Runtime.InteropServices.COMException) { }
if (expr == null || !expr.IsValidValue) {
return FormatMessage(RespType.Error, string.Format("Couldn't evaluate expression: {0}", expression));
}
switch (type) {
case ReqType.Value:
return FormatMessage(RespType.Value, expr.Value);
case ReqType.Type:
return FormatMessage(RespType.Value, expr.Type);
case ReqType.Members: {
var memb = new List<string>();
foreach (Expression c in expr.DataMembers) {
memb.Add(c.Name);
}
return FormatMessage(RespType.Array, string.Join("" + BEL, memb));
}
case ReqType.All: {
var sb = new StringBuilder(expr.Value);
foreach (Expression c in expr.DataMembers) {
sb.Append(string.Format("\n\t{0}: {1}", c.Name, c.Value));
}
return FormatMessage(RespType.Value, sb.ToString());
}
}
return FormatMessage(RespType.Error, "Internal error");
}
/**
* Add block to the cache.
* Either an empty or the LRU block is populated.
* @param block_addr block address
* @param inst_type instruction type
* @return if LRU block is populated, its tag; if empty block is populated, 0
*/
public ulong cache_add(ulong block_addr, ReqType inst_type, ulong pid)
{
cycle++;
//calculate set index
int set_index = (int)(block_addr % set_max);
//empty entry within a set
int empty_entry_index = -1;
//lru entry within a set
ulong return_address = Proc.NULL_ADDRESS;
for (int i = 0; i < Config.N; i ++)
{
count_allocation[i] = 0;
average_allocation_count[i] ++;
}
for (int i = 0; i < Config.proc.cache_assoc; i++)
{
if (valid[set_index,i] == true) {
count_allocation[core_id[set_index, i]] ++;
average_allocation[core_id[set_index, i]] ++;
}
}
//search for empty or lru entry
for (int i = Config.proc.cache_assoc - 1; i >= 0; i--)
{
//make sure not already in cache
if (valid[set_index,i] == true) Debug.Assert(cache[set_index, i] != block_addr);
if (valid[set_index, i] == false) {
if (Config.compute_allocation && (count_allocation[pid] >= (int)Sim.cache_controller.get_allocation((int)pid))) break;
//found empty entry
empty_entry_index = i;
break;
}
}
if (empty_entry_index == -1)
{
if ((Config.ucp || Config.slowdown_allocation || Config.qos_allocation || Config.naive_qos_allocation || Config.compute_allocation) && !Double.IsNaN((double)Sim.cache_controller.get_allocation((int)pid)))
{
if (count_allocation[pid] < (int)Sim.cache_controller.get_allocation((int)pid))
{
for (int j = 0; j < Config.proc.cache_assoc; j ++)
{
if (core_id[set_index,j] != pid)
{
if (Config.poll_filter && Sim.procs[pid].pollution_vector.check_filter(block_addr)) Sim.procs[pid].pollution_vector.clear_pollution_vector(block_addr);
if (Config.poll_filter && pid != core_id[set_index,j]) Sim.procs[core_id[set_index, j]].pollution_vector.set_pollution_vector(cache[set_index, j], (int)pid);
if (dirty[set_index,j]) return_address = cache[set_index,j];
for (int k = j; k < Config.proc.cache_assoc - 1; k ++)
{
cache[set_index,k] = cache[set_index,k+1];
dirty[set_index,k] = dirty[set_index,k+1];
core_id[set_index,k] = core_id[set_index,k+1];
}
cache[set_index,Config.proc.cache_assoc-1] = block_addr;
dirty[set_index,Config.proc.cache_assoc-1] = (inst_type == ReqType.WR);
core_id[set_index,Config.proc.cache_assoc-1] = pid;
break;
}
}
}
else if (Sim.cache_controller.get_allocation((int)pid) != 0)
{
for (int j = 0; j < Config.proc.cache_assoc; j ++)
{
if (core_id[set_index,j] == pid)
{
if (Config.poll_filter && Sim.procs[pid].pollution_vector.check_filter(block_addr)) Sim.procs[pid].pollution_vector.clear_pollution_vector(block_addr);
if (dirty[set_index,j]) return_address = cache[set_index,j];
for (int k = j; k < Config.proc.cache_assoc - 1; k ++)
{
cache[set_index,k] = cache[set_index,k+1];
dirty[set_index,k] = dirty[set_index,k+1];
core_id[set_index,k] = core_id[set_index,k+1];
}
cache[set_index,Config.proc.cache_assoc-1] = block_addr;
dirty[set_index,Config.proc.cache_assoc-1] = (inst_type == ReqType.WR);
core_id[set_index,Config.proc.cache_assoc-1] = pid;
break;
}
}
}
}
else
{
if (dirty[set_index,0]) return_address = cache[set_index,0];
//
if (Config.poll_filter && Sim.procs[pid].pollution_vector.check_filter(block_addr)) Sim.procs[pid].pollution_vector.clear_pollution_vector(block_addr);
if (Config.poll_filter && pid != core_id[set_index,0]) Sim.procs[core_id[set_index, 0]].pollution_vector.set_pollution_vector(cache[set_index, 0], (int)pid);
for (int k = 0; k < Config.proc.cache_assoc - 1; k ++)
{
cache[set_index,k] = cache[set_index,k+1];
dirty[set_index,k] = dirty[set_index,k+1];
core_id[set_index,k] = core_id[set_index,k+1];
}
cache[set_index,Config.proc.cache_assoc-1] = block_addr;
dirty[set_index,Config.proc.cache_assoc-1] = (inst_type == ReqType.WR);
core_id[set_index,Config.proc.cache_assoc-1] = pid;
}
}
else
{
if (Config.poll_filter && Sim.procs[pid].pollution_vector.check_filter(block_addr)) Sim.procs[pid].pollution_vector.clear_pollution_vector(block_addr);
for (int k = empty_entry_index; k < Config.proc.cache_assoc - 1; k ++)
{
cache[set_index,k] = cache[set_index,k+1];
dirty[set_index,k] = dirty[set_index,k+1];
core_id[set_index,k] = core_id[set_index,k+1];
valid[set_index,k] = valid[set_index,k+1];
}
cache[set_index,Config.proc.cache_assoc-1] = block_addr;
dirty[set_index,Config.proc.cache_assoc-1] = (inst_type == ReqType.WR);
core_id[set_index,Config.proc.cache_assoc-1] = pid;
valid[set_index,Config.proc.cache_assoc-1] = true;
}
return return_address;
}
public int has_addr_sampled_set(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++) {
if (valid[set_index,i] == true && cache[set_index, i] == block_addr && set_index%Config.proc.sample == 0) {
return (i + 1000);
}
}
if (set_index % Config.proc.sample == 0) return 1000;
else return 100000;
}
/**
* Searches for a block within the cache.
* If found, sets the dirty bit.
*
* @param block_addr block address
* @param inst_type instruction type
* @return if found, true; otherwise, false
*/
public bool has_addr(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++) {
if (valid[set_index,i] == true && cache[set_index, i] == block_addr) {
//hit
hit++;
if (inst_type == ReqType.WR)
dirty[set_index, i] = true;
ulong temp_cache = cache[set_index, i];
bool temp_dirty = dirty[set_index,i];
ulong temp_core_id = core_id[set_index,i];
bool temp_valid = valid[set_index,i];
for (int j = i; j < Config.proc.cache_assoc - 1; j ++)
{
cache[set_index,j] = cache[set_index,j+1];
dirty[set_index,j] = dirty[set_index,j+1];
core_id[set_index,j] = core_id[set_index,j+1];
valid[set_index,j] = valid[set_index,j+1];
}
cache[set_index,Config.proc.cache_assoc-1] = temp_cache;
dirty[set_index,Config.proc.cache_assoc-1] = temp_dirty;
core_id[set_index,Config.proc.cache_assoc-1] = temp_core_id;
valid[set_index,Config.proc.cache_assoc-1] = temp_valid;
return true;
}
}
miss++;
return false;
}
public void set_prefetch(int pid, ReqType type, ReqType proc_req_type, ulong paddr)
{
//state
this.pid = pid;
this.type = type;
this.proc_req_type = proc_req_type;
this.row_hit = true;
this.actual_addr = paddr;
this.paddr = paddr;
//address
this.block_addr = this.paddr >> Config.proc.block_size_bits;
this.addr = MemMap.translate(this.paddr);
this.is_prefetch = true;
//misc
this.reset();
}
public bool is_q_full(int pid, ReqType rw, uint rid, uint bid)
{
/* read queue */
if (rw == ReqType.RD) {
List<Req> q = readqs[rid, bid];
return q.Count == q.Capacity;
}
/* write queue */
if (mctrl_writeq.Count == mctrl_writeq.Capacity)
return true;
//writeback throttle
bool is_throttle = wbthrottle.is_throttle(pid);
return is_throttle;
}
public int has_addr_sampled_set(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
if (set_index%Config.proc.sample == 0)
{
for (int i = 0; i < Config.proc.cache_assoc; i ++)
{
recency_position[i] = 0;
for (int j = 0; j < Config.proc.cache_assoc; j ++)
{
if (timestamp[set_index, i] >= timestamp[set_index, j] && i != j)
recency_position[i] ++;
}
}
}
//search for block
for (int i = 0; i < Config.proc.cache_assoc; i++) {
if (cache[set_index, i] == block_addr && set_index%Config.proc.sample == 0) {
return (recency_position[i] + 1000);
}
}
if (set_index % Config.proc.sample == 0) return 1000;
else return 100000;
//couldn't find block_addr; miss
}
public static string ReqTypeToString(ReqType rType)
{
switch (rType)
{
case ReqType.CHARACTER_SHEET:
return "characterSheet";
default:
return "";
}
}
public UrlQueueItem(ReqType rType, string url)
{
this.url = url;
this.rType = rType;
}
public static void PurgeRequestQueue(ReqType rType, string url)
{
checkSqlConnections();
string rtype = ReqTypeToString(rType);
lock (cWriterLock)
{
using (SqlCommand cmd = cSqlWriter.CreateCommand())
{
cmd.Parameters.Add("@RTYPE", SqlDbType.VarChar, 32).Value = ReqTypeToString(rType);
cmd.Parameters.Add("@URL", SqlDbType.VarChar).Value = url;
cmd.CommandText = "DELETE FROM armory_RequestQueue WHERE reqType = @RTYPE and url = @URL";
cmd.ExecuteNonQuery();
}
}
}
public bool cache_remove(ulong block_addr, ReqType inst_type)
{
//progress time
cycle++;
//calculate set index
uint set_index = (uint)(block_addr % set_max);
//search for block
for (int i = 0; i < Config.proc.l1_cache_assoc; i++) {
if (cache[set_index, i] == block_addr) {
cache[set_index, i] = Proc.NULL_ADDRESS;
return true;
}
}
return false;
}
