protected override void PreInitialize()
{
_result = new SLVSignal(OutWidth);
_rpipe = new RegPipe(Latency, OutWidth);
Bind(() =>
{
_rpipe.Clk = CLK;
_rpipe.Din = _result;
_rpipe.Dout = S;
});
}
public IEnumerable <RegPipe> InstantiatePipes()
{
_pipeEnSignals = new ISignal[_pipes.Count];
for (int i = 0; i < _pipes.Count; i++)
{
var pi = _pipes[i];
var srcsig = _pipeInSignals[pi.source];
object initval = srcsig.InitialValueObject;
int width = TypeLowering.Instance.GetWireWidth(
TypeDescriptor.GetTypeOf(srcsig.InitialValueObject));
int capa = _pipes[i].capacity;
if (capa == 0)
{
_pipeOutSignals.Add(_pipeInSignals[pi.source]);
continue;
}
var outSignal = _binder.GetSignal(
EPortUsage.Default, "fifo" + pi.source + "_out" + pi.sink + "_" + i,
null, initval);
_pipeOutSignals.Add(outSignal);
bool useEn = capa < pi.delay;
_pipes[i].capacity = capa;
_pipes[i].useEn = useEn;
RegPipe rpipe = new RegPipe(capa, width, useEn)
{
Din = (In <StdLogicVector>)_pipeInSignals[pi.source],
Dout = (Out <StdLogicVector>)outSignal
};
if (capa > 0)
{
rpipe.Clk = (In <StdLogic>)_binder.GetSignal(EPortUsage.Clock, "Clk", null, null);
}
if (useEn)
{
_pipeEnSignals[i] = _binder.GetSignal(
EPortUsage.Default,
"fifoen" + i, null, StdLogic._0);
rpipe.En = (In <StdLogic>)_pipeEnSignals[i];
}
yield return(rpipe);
}
}
protected override void PreInitialize()
{
_t = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PINC = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
POFF = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PH = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
PhaseIn = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
phase3 = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
Dat_in = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
Dat_outOff = new SLVSignal(PhaseWidth)
{
InitialValue = StdLogicVector._0s(PhaseWidth)
};
_RegPipe = new RegPipe(Latency, PhaseWidth)
{
Clk = CLK,
Din = Dat_in,
Dout = Dat_outOff,
};
}
protected override void PreInitialize()
{
int width = OutputWidthHigh - OutputWidthLow + 1;
_pipeIn = new SLVSignal(width);
if (PipeStages > 0)
{
_outPipe = new RegPipe(PipeStages, width);
Bind(() =>
{
_outPipe.Clk = CLK;
_outPipe.Din = _pipeIn;
_outPipe.Dout = P;
});
}
else
{
AddProcess(DrivePIm, _pipeIn);
}
}
protected override void PreInitialize()
{
_quotient = new SLVSignal(DividendAndQuotientWidth);
_remainder = new SLVSignal(FractionWidth);
_quotientOut = new SLVSignal(DividendAndQuotientWidth);
_remainderOut = new SLVSignal(FractionWidth);
_qpipe = new RegPipe(Latency, DividendAndQuotientWidth);
Bind(() =>
{
_qpipe.Clk = CLK;
_qpipe.Din = _quotient;
_qpipe.Dout = _quotientOut;
});
_rpipe = new RegPipe(Latency, FractionWidth);
Bind(() =>
{
_rpipe.Clk = CLK;
_rpipe.Din = _remainder;
_rpipe.Dout = _remainderOut;
});
}
public static void RunTest()
{
DesignContext.Reset();
RegPipe dut = new RegPipe(100, 32, true)
{
Clk = new SLSignal(),
Din = new SLVSignal(32),
Dout = new SLVSignal(32),
En = new SLSignal()
};
DesignContext.Instance.Elaborate();
var fpga = new DefaultXilinxDevice()
{
SpeedGrade = ESpeedGrade._2,
TopLevelComponent = dut
};
fpga.SetDevice(EDevice.xc5vlx110t);
fpga.SetPackage(EPackage.ff1136);
fpga.SpeedGrade = ESpeedGrade._2;
fpga.Synthesize(@"c:\temp\RegPipeTest", "RegPipeTest",
new ModelsimProject(@"c:\temp\RegPipeTest", "RegPipeTest"));
}
