public static void JAL(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.PC += 4;
R4300.InterpretOpcode(R4300.memory.ReadUInt32(Registers.R4300.PC));
Registers.R4300.Reg[31] = Registers.R4300.PC;
Registers.R4300.PC = ((Registers.R4300.PC - 4) & 0xF0000000) | (Desc.Target << 2);
}
public static void DMULTU(OpcodeTable.OpcodeDesc Desc)
{
ulong Res = Registers.R4300.Reg[Desc.op1] * Registers.R4300.Reg[Desc.op2];
Registers.R4300.LO = (uint)(Res & 0x00000000FFFFFFFF);
Registers.R4300.HI = (uint)(Res >> 32);
Registers.R4300.PC += 4;
}
public static void MULT(OpcodeTable.OpcodeDesc Desc)
{
ulong Res = (ulong)((int)Registers.R4300.Reg[Desc.op1] * (int)Registers.R4300.Reg[Desc.op2]);
Registers.R4300.LO = (uint)(Res & 0x00000000FFFFFFFF);
Registers.R4300.HI = (uint)(Res >> 32);
Registers.R4300.PC += 4;
}
public static void BLTZ(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.PC += 4;
R4300.InterpretOpcode(R4300.memory.ReadUInt32(Registers.R4300.PC));
if ((long)Registers.R4300.Reg[Desc.op1] <= 0)
{
Registers.R4300.PC += (uint)((short)((Desc.Imm - 1) << 2));
}
}
public static void SLTU(OpcodeTable.OpcodeDesc Desc)
{
if (Registers.R4300.Reg[Desc.op1] < Registers.R4300.Reg[Desc.op2])
{
Registers.R4300.Reg[Desc.op3] = 1;
}
else
{
Registers.R4300.Reg[Desc.op3] = 0;
}
Registers.R4300.PC += 4;
}
public static void SLTI(OpcodeTable.OpcodeDesc Desc)
{
if ((long)Registers.R4300.Reg[Desc.op1] < (short)Desc.Imm)
{
Registers.R4300.Reg[Desc.op2] = 1;
}
else
{
Registers.R4300.Reg[Desc.op2] = 0;
}
Registers.R4300.PC += 4;
}
public static void BEQL(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.PC += 4;
if ((long)Registers.R4300.Reg[Desc.op1] == (long)Registers.R4300.Reg[Desc.op2])
{
R4300.InterpretOpcode(R4300.memory.ReadUInt32(Registers.R4300.PC));
Registers.R4300.PC += (uint)((short)((Desc.Imm - 1) << 2));
}
else
{
Registers.R4300.PC += 4;
}
}
public static void TLBR(OpcodeTable.OpcodeDesc Desc)
{
TLB.ReadTLBEntry();
Registers.R4300.PC += 4;
}
public static void TLBP(OpcodeTable.OpcodeDesc Desc)
{
TLB.ProbeTLB();
Registers.R4300.PC += 4;
}
public static void TLBWR(OpcodeTable.OpcodeDesc Desc)
{
TLB.WriteTLBEntryRandom();
Registers.R4300.PC += 4;
}
public static void TLBWI(OpcodeTable.OpcodeDesc Desc)
{
TLB.WriteTLBEntryIndexed();
Registers.R4300.PC += 4;
}
public static void SRL(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op3] = (uint)Registers.R4300.Reg[Desc.op2] >> Desc.op4;
Registers.R4300.PC += 4;
}
public static void ADDIU(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] = (uint)((int)Registers.R4300.Reg[Desc.op1] + (short)Desc.Imm);
Registers.R4300.PC += 4;
}
public static void JR(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.PC += 4;
R4300.InterpretOpcode(R4300.memory.ReadUInt32(Registers.R4300.PC));
Registers.R4300.PC = (uint)(Registers.R4300.Reg[Desc.op1] & 0xFFFFFFFF);
}
public static void NOP(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.PC += 4; // The NOP Instruction, do nothing.
}
public static void XOR(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op3] = (uint)Registers.R4300.Reg[Desc.op1] ^ (uint)Registers.R4300.Reg[Desc.op2];
Registers.R4300.PC += 4;
}
public static void SUBU(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op3] = (uint)((int)Registers.R4300.Reg[Desc.op1] - (int)Registers.R4300.Reg[Desc.op2]);
Registers.R4300.PC += 4;
}
public static void SUB(OpcodeTable.OpcodeDesc Desc)
{
// TODO: Correctly check for underflow
SUBU(Desc);
}
public static void ADD(OpcodeTable.OpcodeDesc Desc)
{
// TODO: Correctly check for Overflow and Underflow
ADDU(Desc);
}
public static void SRA(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op3] = (ulong)((int)Registers.R4300.Reg[Desc.op2] >> Desc.op4);
Registers.R4300.PC += 4;
}
public static void LB(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] = (byte)R4300.memory.ReadInt8((uint)((int)Registers.R4300.Reg[Desc.op1] + (short)Desc.Imm));
Registers.R4300.PC += 4;
}
public static void LWU(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] = R4300.memory.ReadUInt32((uint)((int)Registers.R4300.Reg[Desc.op1] + (short)Desc.Imm));
Registers.R4300.PC += 4;
}
public static void LUI(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] = (uint)(Desc.Imm << 16);
Registers.R4300.PC += 4;
}
public static void SRLV(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op3] = (uint)Registers.R4300.Reg[Desc.op2] >> (byte)(Registers.R4300.Reg[Desc.op1] & 0x0000001F);
Registers.R4300.PC += 4;
}
public static void LDR(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] >>= 32;
Registers.R4300.Reg[Desc.op2] |= (ulong)R4300.memory.ReadInt64((uint)((int)Registers.R4300.Reg[Desc.op1] + (short)Desc.Imm)) >> 32;
Registers.R4300.PC += 4;
}
public static void MFHI(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op3] = Registers.R4300.HI;
Registers.R4300.PC += 4;
}
public static void LWR(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] &= 0xFFFFFFFFFFFF0000;
Registers.R4300.Reg[Desc.op2] |= (uint)R4300.memory.ReadInt32((uint)((int)Registers.R4300.Reg[Desc.op1] + (short)Desc.Imm)) >> 16;
Registers.R4300.PC += 4;
}
public static void ORI(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.Reg[Desc.op2] = (uint)Registers.R4300.Reg[Desc.op1] | Desc.Imm;
Registers.R4300.PC += 4;
}
public static void SH(OpcodeTable.OpcodeDesc Desc)
{
R4300.memory.WriteUInt16((uint)((int)Registers.R4300.Reg[Desc.op1] + (short)Desc.Imm), (ushort)Registers.R4300.Reg[Desc.op2]);
Registers.R4300.PC += 4;
}
public static void MTLO(OpcodeTable.OpcodeDesc Desc)
{
Registers.R4300.LO = Registers.R4300.Reg[Desc.op1];
Registers.R4300.PC += 4;
}
