/// <summary>
/// Классификатор
/// </summary>
/// <param name="inpDim">Размерность входа</param>
public Classifier(int inpDim)
{
InpDim = inpDim;
net.Add(new FullBipolyareSigmoid(InpDim, 5));
net.Add(new Softmax(2));
mNNW = new MenegerNNW(net, vectorClasses);
}
/// <summary>
/// Данные для визуализации
/// </summary>
/// <param name="n">Число классов</param>
/// <returns></returns>
public Vector[] DataVisual(int n)
{
Net net = new Net(rnd);
net.Add(new LinearLayer(this[0].InpVector.N, 2));
net.Add(new Softmax(n));
net.LerningRate = 0.0001;
net.Moment = 0;
MenegerNNW mnnw = new MenegerNNW(net, this);
mnnw.Train(2);
Vector[] vects = new Vector[2 * n];
Vector nnwOut;
List <double>[] x = new List <double> [n];
List <double>[] y = new List <double> [n];
for (int i = 0; i < n; i++)
{
x[i] = new List <double>();
y[i] = new List <double>();
}
for (int i = 0; i < Count; i++)
{
for (int j = 0; j < n; j++)
{
nnwOut = net._layers[0].Output(this[i].InpVector);
if (this[i].ClassMark == j)
{
x[j].Add(nnwOut[0]);
y[j].Add(nnwOut[1]);
}
}
}
for (int i = 0, k = 0; i < n; i++)
{
vects[k++] = Vector.ListToVector(x[i]);
vects[k++] = Vector.ListToVector(y[i]);
}
return(vects);
}
public void AddItem(InvoiceLine item)
{
_items.Add(item);
Net = Net.Add(item.Net);
Gros = Gros.Add(item.Gros);
}
private void Add(decimal capitalLong, decimal capitalShort)
{
Long.Add(capitalLong);
Short.Add(capitalShort);
Gross.Add(capitalLong + capitalShort);
Net.Add(capitalLong - capitalShort);
}
public static Net Convolution(
this Net net,
int[] weightLengths,
int kernelCount = 1,
int[] strideArray = null)
{
var inputSize = net.OutputSize;
var dimensionCount = inputSize.Dimensions.Length;
strideArray = strideArray ?? Enumerable.Range(0, dimensionCount)
.Select(_ => 1)
.ToArray();
if (strideArray.Length != dimensionCount)
{
throw new ArgumentOutOfRangeException($"Stride array dimensions ({strideArray.Length}) must be the same as the input ({dimensionCount}).");
}
var paddingArray = weightLengths
.Select(l => (l - 1) / 2)
.ToArray();
net.Add(new ConvolutionalLayer(
inputSize,
weightLengths,
kernelCount,
strideArray,
paddingArray));
return(net);
}
/// <summary>
/// Множественная регрессия
/// </summary>
/// <param name="vectsInp"></param>
/// <param name="vectOutp"></param>
public MultipleRegressionNNW(Vector[] vectsInp, Vector vectOutp)
{
net.Add(new LinearLayer(vectsInp[0].N, 1));
net.LerningRate = 0.001;
_Xs = new Vector[vectOutp.N];
_Xs = vectsInp;
_Ys = vectOutp;
}
public bool AddGndPrimitive(Net net)
{
TCLInstance gnd = new TCLInstance();
gnd.Name = "gnd_for_" + net.Name;
Tile any = TileSelectionManager.Instance.GetSelectedTiles().Where(t => t.Slices.Count > 0).First();
gnd.Location = any.Location;
gnd.SliceName = any.Slices[0].SliceName;
gnd.BELType = "GND";
gnd.OmitPlaceCommand = true;
Add(gnd);
NetOutpin outpin = new NetOutpin();
outpin.InstanceName = gnd.Name;
outpin.SlicePort = "G";
net.Add(outpin);
return(true);
/*
* TCLInstance vcc = new TCLInstance();
* vcc.Name = "vcc_for_" + blockerNet.Name;
* Tile any = FPGA.TileSelectionManager.Instance.GetSelectedTiles().First();
* vcc.Location = any.Location;
* vcc.BELType = "VCC";
* vcc.OmitPlaceCommand = true;
* nlc.Add(vcc);
*
* NetOutpin outpin = new NetOutpin();
* outpin.InstanceName = vcc.Name;
* outpin.SlicePort = "P";
* blockerNet.Add(outpin);
*
* return true;
* */
}
public static Net ConvolutionTranspose(
this Net net,
int[] weightLengths,
int kernelCount = 1)
{
var inputSize = net.OutputSize;
var strideArray = Enumerable.Range(0, inputSize.Dimensions.Length)
.Select(_ => 1)
.ToArray();
var paddingArray = weightLengths
.Select(l => l - 1)
.ToArray();
net.Add(new ConvolutionalLayer(
inputSize,
weightLengths,
kernelCount,
strideArray,
paddingArray));
return(net);
}
public static bool AddXDLOutpin(Net blockerNet, Tile t, int sliceNumber)
{
foreach (Port sliceOutPort in GetAllDrivers(t, sliceNumber))
{
foreach (Port target in t.SwitchMatrix.GetDrivenPorts(sliceOutPort).Where(drivenPort => !t.IsPortBlocked(drivenPort) && !BlockerSettings.Instance.SkipPort(drivenPort)))
{
List <Location> locations = new List <Location>();
foreach (Location loc in Navigator.GetDestinations(t, target))
{
locations.Add(loc);
}
if (locations.Count < 1)
{
continue;
}
Tile neighbour = locations[0].Tile;
Port driverOnNeighbourTile = locations[0].Pip;
if (neighbour.IsPortBlocked(driverOnNeighbourTile))
{
continue;
}
Port beginPip = neighbour.SwitchMatrix.GetDrivenPorts(driverOnNeighbourTile).FirstOrDefault(p => !neighbour.IsPortBlocked(p));
if (beginPip == null)
{
continue;
}
// arc on CLB
if (blockerNet is XDLNet)
{
((XDLNet)blockerNet).Add(t, sliceOutPort, target);
}
else
{
// TODO
}
BlockPort(t, sliceOutPort);
BlockPort(t, target);
// ouptin on CLB
NetOutpin outpin = new NetOutpin();
outpin.InstanceName = t.Slices[sliceNumber].SliceName;
outpin.SlicePort = NetPin.GetSlicePortString(sliceOutPort.Name);
blockerNet.Add(outpin);
// arc in INT
if (blockerNet is XDLNet)
{
((XDLNet)blockerNet).Add(neighbour, driverOnNeighbourTile, beginPip);
}
else
{
// TODO
}
BlockPort(neighbour, driverOnNeighbourTile);
BlockPort(neighbour, beginPip);
return(true);
}
}
return(false);
}
public override void Do()
{
// fetch all clbs
Queue <Tile> allINTs = new Queue <Tile>();
foreach (Tile tile in FPGA.FPGA.Instance.GetAllTiles())
{
if (Regex.IsMatch(tile.Location, "^INT_BRAM_"))
{
allINTs.Enqueue(tile);
}
}
// get all ports
SortedDictionary <Port, bool> allPorts = new SortedDictionary <Port, bool>();
Tile interConnectTile = allINTs.Peek();
// for all ports
foreach (Port p in interConnectTile.SwitchMatrix.GetAllPorts())
{
if (Regex.IsMatch(p.ToString(), "(N|E|S|W)(E|L|N|R|W|S)(1|2|4)B[0-3]") && !allPorts.ContainsKey(p))
{
allPorts.Add(p, false);
}
if (Regex.IsMatch(p.ToString(), @"^LOGICIN\d+") && !allPorts.ContainsKey(p))
{
//allPorts.Add(p, false);
}
}
// all nets have the same source
foreach (Port drivenPorts in allPorts.Keys)
{
Tile currentInt = allINTs.Dequeue();
String interfaceLocation = Regex.Replace(currentInt.Location, "BRAM", "INTERFACE");
if (!FPGA.FPGA.Instance.Contains(interfaceLocation))
{
continue;
}
Tile currentCLB = FPGA.FPGA.Instance.GetTile(interfaceLocation);
foreach (Port source in currentInt.SwitchMatrix.GetAllDrivers())
{
if (currentInt.SwitchMatrix.Contains(source, drivenPorts) && Regex.IsMatch(source.ToString(), "LOGICOUT"))
{
Net next = new Net(drivenPorts.ToString());
//CLEXL_LOGICOUT0
String clbPrefix = currentCLB.Location.Split('_')[0];
String clbPort = clbPrefix + "_INTERFACE_" + source;
// get lut port
Port lutOutPort = null;
foreach (Port p in currentCLB.SwitchMatrix.GetAllDrivers())
{
if (currentCLB.SwitchMatrix.Contains(p, new Port(clbPort)))
{
lutOutPort = p;
break;
}
}
next.Add(currentCLB, lutOutPort, new Port(clbPort));
next.Add(currentInt, source, drivenPorts);
Objects.MacroManager.Instance.CurrentMacro.Add(next, false);
//CommandExecuter.Instance.Execute(new SetFocus(currentCLB.Location));
//CommandExecuter.Instance.Execute(new AddSlice(0));
//CommandExecuter.Instance.Execute(new AddSlice(1));
break;
}
}
}
}
public static Net Dense(this Net net, Size outputSize)
{
net.Add(new DenseLayer(net.OutputSize, outputSize));
return(net);
}
public static Net Relu(this Net net)
{
net.Add(new Relu(net.OutputSize));
return(net);
}
public static Net Sigmoid(this Net net)
{
net.Add(new Sigmoid(net.OutputSize));
return(net);
}
/// <summary>
/// Линейный автокодировщик
/// </summary>
/// <param name="inputs">Размерность исходного пространства</param>
/// <param name="outps">Размерность нового пространства</param>
public LinearAutocoder(int inputs, int outps)
{
ll = new LinearLayer(inputs, outps);
net.Add(ll);
net.Add(new FullBipolyareSigmoid(inputs));
}
public override void Do()
{
// fetch all clbs
Queue <Tile> allCLBs = new Queue <Tile>();
foreach (Tile tile in FPGA.FPGA.Instance.GetAllTiles())
{
if (Regex.IsMatch(tile.Location, FPGA.Types.GetCLBRegex()))
{
allCLBs.Enqueue(tile);
}
}
// get interconnect tile
SortedDictionary <Port, bool> allPorts = new SortedDictionary <Port, bool>();
// get all port filter
String portFilter = "";
String srcPortFilter = "";
if (FPGA.FPGA.Instance.Family.Equals(Types.FPGAFamily.Spartan6))
{
portFilter = "(N|E|S|W)(E|L|N|R|W|S)(1|2|4)B[0-3]";
srcPortFilter = "LOGICOUT";
}
else if (FPGA.FPGA.Instance.Family.Equals(Types.FPGAFamily.Kintex7))
{
portFilter = "(N|E|S|W)(E|L|N|R|W|S)(1|2|4)BEG[0-3]";
srcPortFilter = "LOGIC_OUT";
}
else
{
throw new ArgumentException("Current FPGA familiy not implemented in AllArcs");
}
// look for a "typical" interconnect tile from which we store all ports
foreach (Tile t in allCLBs)
{
Tile interConnectTile = GetInterconnectTile(allCLBs.Peek());
// for all ports
foreach (Port p in interConnectTile.SwitchMatrix.GetAllPorts())
{
if (Regex.IsMatch(p.ToString(), portFilter) && !allPorts.ContainsKey(p))
{
allPorts.Add(p, false);
}
}
// stop after the first CLB after adding some ports
if (allPorts.Count > 0)
{
break;
}
}
// all nets have the same source
foreach (Port drivenPorts in allPorts.Keys)
{
Tile currentCLB = allCLBs.Dequeue();
Tile currentInt = this.GetInterconnectTile(currentCLB);
foreach (Port source in currentInt.SwitchMatrix.GetAllDrivers())
{
if (currentInt.SwitchMatrix.Contains(source, drivenPorts) && Regex.IsMatch(source.ToString(), srcPortFilter))
{
Net next = new Net(drivenPorts.ToString());
//CLEXL_LOGICOUT0
String clbPort = this.GetCLBPort(currentCLB, source);
// get lut port
Port lutOutPort = null;
foreach (Port p in currentCLB.SwitchMatrix.GetAllDrivers())
{
if (currentCLB.SwitchMatrix.Contains(p, new Port(clbPort)))
{
lutOutPort = p;
break;
}
}
if (lutOutPort == null)
{
}
next.Add(currentCLB, lutOutPort, new Port(clbPort));
next.Add(currentInt, source, drivenPorts);
Objects.MacroManager.Instance.CurrentMacro.Add(next, false);
CommandExecuter.Instance.Execute(new SetFocus(currentCLB.Location));
CommandExecuter.Instance.Execute(new AddSlice(0));
CommandExecuter.Instance.Execute(new AddSlice(1));
break;
}
}
}
}
public static Net TanH(this Net net)
{
net.Add(new TanH(net.OutputSize));
return(net);
}