/// <summary>
/// Transfer Processor requests into Memory requests
/// </summary>
/// <param name="pro_req_">processor request to transfer</param>
/// <returns></returns>
public static MemRequest transfer(ProcRequest pro_req_)
{
MemRequest trans = new MemRequest();
trans.address = MemorySelector.resize(pro_req_.actual_addr);
trans.data = 0; //actully we need no data here, but we'll take it in the future.
trans.block_addr = pro_req_.block_addr;
trans.pid.Add(pro_req_.pid);
trans.cycle = pro_req_.cycle;
switch (pro_req_.type)
{
case RequestType.READ:
trans.memtype = MemReqType.READ;
break;
case RequestType.WRITE:
trans.memtype = MemReqType.WRITE;
break;
case RequestType.FLUSH:
trans.memtype = MemReqType.FLUSH;
break;
default:
trans.memtype = MemReqType.RETURN_DATA;
break;
}
return(trans);
}
public SpinLock()
{
page_index = MemorySelector.get_RAM_size() / size + 1;
lock_table = new List <string>();
//foreach block entry, set lock table false.
for (int i = 0; i < (Int64)(page_index / 64); i++)
{
lock_table.Add(empty);
}
}
/// <summary>
/// Set data locked.
/// </summary>
/// <param name="addr">Used address</param>
public void setlock(UInt64 addr)
{
//resize address in case of address is out of range.
var addr_ = MemorySelector.resize(addr);
Int64 index_all = (Int64)(addr_ / size);
int index = (int)(index_all / 64);
int mod = (int)(index_all % 64);
setbit(mod, index, true);
total_set_lock++;
}
public void relese_lock(UInt64 addr)
{
var addr_ = MemorySelector.resize(addr);
var index = addr_ / size;
Int32 i = (Int32)(index / 64);
int j = (int)(index % 64);
// return lock_table[(Int32)(addr / page_index)];
var item = lock_table[i].ToArray();
item[j] = FALSE;
lock_table[i] = new string(item);
total_unlock++;
}
/// <summary>
/// Things ctrl done every cycle.
/// </summary>
public static void Step()
{
cycle++;
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine();
DEBUG.WriteLine("---------PIM Memory Controller [" + id + "] Update [Cycle " + cycle + "]------------");
}
for (int i = 0; i < wait_queue.Count(); i++)
{
ProcRequest peek = wait_queue[i];
if (peek.cycle + (UInt64)Config.mc_latency <= cycle - 1)
{
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine("-- Issue ProcRequest : [" + peek.type + "] [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]");
}
if (PIMConfigs.Consistency_Model == Consistency.SpinLock)
{
//if (Config.DEBUG_MTRL)
// DEBUG.WriteLine("-- Use Coherence : [" + Config.pim_config.Consistency_Model.ToString() + "]");
Coherence.spin_lock.setlock(peek.actual_addr);
//when pim units start to perform, flush all relative data in the host core
if (!Coherence.flush(peek.block_addr))
{
Coherence.spin_lock.relese_lock(peek.actual_addr);
DEBUG.WriteLine("-- Waiting Host cores flushing data : [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]");
continue;
}
send_queue[MemorySelector.get_id(wait_queue[i].actual_addr)].Enqueue(transfer(wait_queue[i]));
wait_queue.RemoveAt(i);
i--;
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine("-- Sent ProcRequest : [" + peek.type + "] [0x" + peek.block_addr.ToString("X") + "] [0x" + peek.actual_addr.ToString("X") + "]");
}
}
}
}
if (Config.DEBUG_MTRL)
{
DEBUG.WriteLine();
}
}
/// <summary>
/// Get current lock state of an address.
/// </summary>
/// <param name="addr">Used address</param>
/// <returns></returns>
public bool get_lock_state(UInt64 addr)
{
total_get_lock++;
var addr_ = MemorySelector.resize(addr);
var index = addr_ / size;
Int32 i = (Int32)(index / 64);
int j = (int)(index % 64);
// return lock_table[(Int32)(addr / page_index)];
if ((lock_table[i].ToArray())[j] == TRUE)
{
total_stalled++;
return(true);
}
total_unstalled++;
return(false);
}
public PIMSimulator(string[] args)
{
initAllconfigs(args);
trace = new TraceFetcher();
ins_p = new InsPartition();
pg = new PageConverter();
if (Config.shared_cache)
{
shared_cache = new Shared_Cache();
}
proc = new List <Proc>();
for (int i = 0; i < Config.N; i++)
{
Proc to_add = new Proc(ref ins_p, i);
if (Config.shared_cache)
{
to_add.attach_shared_cache(ref shared_cache);
}
to_add.attach_tlb(ref pg);
proc.Add(to_add);
}
int count = 0;
foreach (var item in Config.memory)
{
if (item.Key.Equals("HMC"))
{
var tp = new HMCMem(count++) as MemObject;
MemorySelector.add(item.Value, ref tp);
}
else
{
if (item.Key.Equals("DRAM") || item.Key.Equals("PCM"))
{
var tp = new DDRMem(count++) as MemObject;
MemorySelector.add(item.Value, ref tp);
}
else
{
//error
DEBUG.Error("Unknown Memory Type.");
Environment.Exit(3);
}
}
}
Mctrl.init_queue();
PIMMctrl.init_queue();
pim = new PIM.PIM(ref ins_p);
Coherence.init();
Coherence.linkproc(proc);
GlobalTimer.InitClock();
BuildTopology();
}
