public PCIeMemory(IPCIeRouter parent, uint size) : base(parent)
{
this.memory = new uint[size / 4];
for (var i = 0u; i < HeaderType.MaxNumberOfBARs(); ++i)
{
AddBaseAddressRegister(i, new MemoryBaseAddressRegister(size, MemoryBaseAddressRegister.BarType.LocateIn32Bit, true));
}
}
protected PCIeBasePeripheral(IPCIeRouter parent, HeaderType headerType)
{
if (!IsHeaderAcceptable(headerType))
{
throw new ConstructionException($"Currently only devices of type {HeaderType.Bridge} or {HeaderType.Endpoint} are supported.");
}
this.parent = parent;
this.HeaderType = headerType;
this.baseAddressRegisters = new BaseAddressRegister[headerType.MaxNumberOfBARs()];
var registerMap = new Dictionary <long, DoubleWordRegister>
{
{ (long)Registers.DeviceAndVendorId, new DoubleWordRegister(this)
.WithValueField(0, 16, FieldMode.Read, valueProviderCallback: _ => VendorId)
.WithValueField(16, 16, FieldMode.Read, valueProviderCallback: _ => DeviceId) },
{ (long)Registers.StatusAndConfiguration, new DoubleWordRegister(this) //unsupported fields do not have to be implemented. Maybe we should move it to inheriting classes?
//First 16 bits: command register. RW. Writing 0 to these fields should effectively disable all accesses but the configuration accesses
.WithTaggedFlag("I/O Space", 0)
.WithTaggedFlag("Memory Space", 1)
.WithTaggedFlag("Bus Master", 2)
.WithTaggedFlag("Special Cycles", 3)
.WithTaggedFlag("Memory Write and Invalidate Enable", 4)
.WithTaggedFlag("VGA Palette Snoop", 5)
.WithTaggedFlag("Parity Error Response", 6)
.WithReservedBits(7, 1)
.WithTaggedFlag("SERR# Enable", 8)
.WithTaggedFlag("Fast Back-to-Back Enable", 9)
.WithTaggedFlag("Interrupt Disable", 10)
.WithReservedBits(11, 8)
//Second 16 bits: status register. W1C.
.WithTaggedFlag("Interrupt Status", 19)
.WithFlag(20, FieldMode.Read, valueProviderCallback: _ => capabilities.Any(), name: "Capabilities List")
.WithTaggedFlag("66 MHz Capabale", 21)
.WithReservedBits(22, 1)
.WithTaggedFlag("Fast Back-to-Back capable", 23)
.WithTaggedFlag("Master Data Parity Error", 24)
.WithTag("DEVSEL Timing", 25, 2)
.WithTaggedFlag("Signaled Target Abort", 27)
.WithTaggedFlag("Received Target Abort", 28)
.WithTaggedFlag("Received Master Abort", 29)
.WithTaggedFlag("Signaled System Error", 30)
.WithTaggedFlag("Detected Parity Error", 31) },
{ (long)Registers.ClassCode, new DoubleWordRegister(this)
.WithValueField(0, 8, FieldMode.Read, valueProviderCallback: _ => RevisionId)
.WithValueField(16, 16, FieldMode.Read, valueProviderCallback: _ => ClassCode) },
{ (long)Registers.Header, new DoubleWordRegister(this)
.WithTag("Cacheline Size", 0, 8)
.WithTag("Latency Timer", 8, 8)
.WithEnumField(16, 8, FieldMode.Read, valueProviderCallback: (HeaderType _) => headerType)
.WithTag("BIST", 24, 8) },
{ (long)Registers.Capabilities, new DoubleWordRegister(this)
.WithValueField(0, 8, FieldMode.Read, valueProviderCallback: _ => capabilities.FirstOrDefault().Key) },
};
registers = new DoubleWordRegisterCollection(this, registerMap);
AddCapability(0x80, new PCIeCapability(this));
}
//todo: add registers enum
public PCIeEndpoint(IPCIeRouter parent) : base(parent, HeaderType.Endpoint)
{
}
public PCIeRootComplex(IPCIeRouter parent) : base(parent)
{
}
//todo: add registers enum
public PCIeBridge(IPCIeRouter parent) : base(parent, HeaderType.Bridge)
{
}
