public static void ThrowIfCrashed(eCellType[] fieldMatrix, Position position)
{
bool isCrashed = position.row > 7 || position.col > 7;
if (isCrashed)
{
throw new CrashedInWallException();
}
eCellType type;
FieldMatrix.GetCellTypeByPosition(fieldMatrix, position, out type);
var crashTypes = new FPGA.Collections.ReadOnlyDictionary <eCellType, bool>()
{
{ eCellType.SnakeHead, true },
{ eCellType.SnakeDown, true },
{ eCellType.SnakeUp, true },
{ eCellType.SnakeLeft, true },
{ eCellType.SnakeRight, true }
};
isCrashed = crashTypes[type];
if (isCrashed)
{
throw new CrashedInSnakeException();
}
}
public static void DrawFieldMatrix(
uint baseColor,
eCellType[] matrix,
out bool DOUT)
{
uint[] buff = new uint[matrix.Length];
uint color = 0;
for (byte idx = 0; idx < buff.Length; idx++)
{
eCellType value = eCellType.None;
value = matrix[idx];
FPGA.Collections.ReadOnlyDictionary <eCellType, uint> mapColors = new FPGA.Collections.ReadOnlyDictionary <eCellType, uint>()
{
{ eCellType.SnakeUp, baseColor },
{ eCellType.SnakeDown, baseColor },
{ eCellType.SnakeLeft, baseColor },
{ eCellType.SnakeRight, baseColor },
{ eCellType.SnakeHead, baseColor * 2 },
{ eCellType.NextPart, baseColor << 8 },
{ eCellType.RedCross, baseColor << 16 },
{ eCellType.GreenCross, baseColor << 8 },
};
color = mapColors[value];
buff[idx] = color;
}
Draw(buff, out DOUT);
}
public static void WriteData(
FPGA.Register <ulong> a00, FPGA.Register <ulong> a01, FPGA.Register <ulong> a02, FPGA.Register <ulong> a03, FPGA.Register <ulong> a04,
FPGA.Register <ulong> a05, FPGA.Register <ulong> a06, FPGA.Register <ulong> a07, FPGA.Register <ulong> a08, FPGA.Register <ulong> a09,
FPGA.Register <ulong> a10, FPGA.Register <ulong> a11, FPGA.Register <ulong> a12, FPGA.Register <ulong> a13, FPGA.Register <ulong> a14,
FPGA.Register <ulong> a15, FPGA.Register <ulong> a16, FPGA.Register <ulong> a17, FPGA.Register <ulong> a18, FPGA.Register <ulong> a19,
FPGA.Register <ulong> a20, FPGA.Register <ulong> a21, FPGA.Register <ulong> a22, FPGA.Register <ulong> a23, FPGA.Register <ulong> a24,
out bool TXD)
{
TXD = true;
FPGA.Collections.ReadOnlyDictionary <byte, ulong> mapItems = new FPGA.Collections.ReadOnlyDictionary <byte, ulong>()
{
{ 0, a00 }, { 1, a01 }, { 2, a02 }, { 3, a03 }, { 4, a04 },
{ 5, a05 }, { 6, a06 }, { 7, a07 }, { 8, a08 }, { 9, a09 },
{ 10, a10 }, { 11, a11 }, { 12, a12 }, { 13, a13 }, { 14, a14 },
{ 15, a15 }, { 16, a16 }, { 17, a17 }, { 18, a18 }, { 19, a19 },
{ 20, a20 }, { 21, a21 }, { 22, a22 }, { 23, a23 }, { 24, a24 },
};
for (byte pos = 0; pos < 25; pos++)
{
ulong tmp = 0;
tmp = mapItems[pos];
for (byte j = 0; j < 8; j++)
{
UART.RegisteredWrite(115200, (byte)tmp, out TXD);
tmp = tmp >> 8;
}
}
}
public static void Lookup(byte key, out byte value)
{
FPGA.Collections.ReadOnlyDictionary <byte, byte> items = new FPGA.Collections.ReadOnlyDictionary <byte, byte>()
{
{ 0, 1 },
{ 1, 2 },
{ 2, 4 },
{ 3, 10 },
{ 4, 15 }
};
value = items[key];
}
public static void CellTypeToDirectionType(
eCellType cellType,
ref eDirectionType directionType)
{
var lookup = new FPGA.Collections.ReadOnlyDictionary <eCellType, eDirectionType>()
{
{ eCellType.SnakeUp, eDirectionType.Up },
{ eCellType.SnakeDown, eDirectionType.Down },
{ eCellType.SnakeLeft, eDirectionType.Left },
{ eCellType.SnakeRight, eDirectionType.Right }
};
directionType = lookup[cellType];
}
public static void KeyCodeToDirection(
KeypadKeyCode keyCode,
ref eDirectionType direction)
{
var lookup = new FPGA.Collections.ReadOnlyDictionary <KeypadKeyCode, eDirectionType>()
{
{ KeypadKeyCode.D2, eDirectionType.Up },
{ KeypadKeyCode.D8, eDirectionType.Down },
{ KeypadKeyCode.D4, eDirectionType.Left },
{ KeypadKeyCode.D6, eDirectionType.Right }
};
direction = lookup[keyCode];
}
public static void EncodeValue(byte value, out byte encoded)
{
FPGA.Collections.ReadOnlyDictionary <byte, byte> lookup = new FPGA.Collections.ReadOnlyDictionary <byte, byte>()
{
{ 0, 0xFC },
{ 1, 0x60 },
{ 2, 0xDA },
{ 3, 0xF2 },
{ 4, 0x66 },
{ 5, 0xB6 },
{ 6, 0xBE },
{ 7, 0xE0 },
{ 8, 0xFE },
{ 9, 0xF6 },
};
encoded = lookup[value];
}
public static void ReadASCIICode(
FPGA.OutputSignal <bool> K7,
FPGA.OutputSignal <bool> K6,
FPGA.OutputSignal <bool> K5,
FPGA.OutputSignal <bool> K4,
FPGA.InputSignal <bool> K3,
FPGA.InputSignal <bool> K2,
FPGA.InputSignal <bool> K1,
FPGA.InputSignal <bool> K0,
out KeypadKeyCode code
)
{
byte rawCode = 0;
ReadCode(K7, K6, K5, K4, K3, K2, K1, K0, out rawCode);
FPGA.Collections.ReadOnlyDictionary <byte, Drivers.KeypadKeyCode> asciiLookup = new FPGA.Collections.ReadOnlyDictionary <byte, Drivers.KeypadKeyCode>()
{
{ 0, Drivers.KeypadKeyCode.None },
{ 1, Drivers.KeypadKeyCode.D1 },
{ 2, Drivers.KeypadKeyCode.D2 },
{ 3, Drivers.KeypadKeyCode.D3 },
{ 4, Drivers.KeypadKeyCode.STOP },
{ 5, Drivers.KeypadKeyCode.D4 },
{ 6, Drivers.KeypadKeyCode.D5 },
{ 7, Drivers.KeypadKeyCode.D6 },
{ 8, Drivers.KeypadKeyCode.GO },
{ 9, Drivers.KeypadKeyCode.D7 },
{ 10, Drivers.KeypadKeyCode.D8 },
{ 11, Drivers.KeypadKeyCode.D9 },
{ 12, Drivers.KeypadKeyCode.LOCK },
{ 13, Drivers.KeypadKeyCode.ENT },
{ 14, Drivers.KeypadKeyCode.D0 },
{ 15, Drivers.KeypadKeyCode.ESC },
{ 16, Drivers.KeypadKeyCode.PWR },
};
code = asciiLookup[rawCode];
}
public static void ReadCode(
FPGA.OutputSignal <bool> K7,
FPGA.OutputSignal <bool> K6,
FPGA.OutputSignal <bool> K5,
FPGA.OutputSignal <bool> K4,
FPGA.InputSignal <bool> K3,
FPGA.InputSignal <bool> K2,
FPGA.InputSignal <bool> K1,
FPGA.InputSignal <bool> K0,
out byte code
)
{
byte colCode = 1 << 4;
Func <bool> k7bit = () => FPGA.Config.Bit(colCode, 3);
Func <bool> k6bit = () => FPGA.Config.Bit(colCode, 2);
Func <bool> k5bit = () => FPGA.Config.Bit(colCode, 1);
Func <bool> k4bit = () => FPGA.Config.Bit(colCode, 0);
Func <byte> rowCode = () => (byte)((K3 << 3) | (K2 << 2) | (K1 << 1) | K0);
FPGA.Config.Link(k7bit, K7);
FPGA.Config.Link(k6bit, K6);
FPGA.Config.Link(k5bit, K5);
FPGA.Config.Link(k4bit, K4);
while (colCode > 0)
{
colCode = (byte)(colCode >> 1);
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(1));
if (rowCode() != 0)
{
break;
}
}
byte row = 0, col = 0;
FPGA.Collections.ReadOnlyDictionary <byte, byte> colLookup = new FPGA.Collections.ReadOnlyDictionary <byte, byte>()
{
{ 8, 1 },
{ 4, 2 },
{ 2, 3 },
{ 1, 4 }
};
col = colLookup[colCode];
FPGA.Collections.ReadOnlyDictionary <byte, byte> rowLookup = new FPGA.Collections.ReadOnlyDictionary <byte, byte>()
{
{ 1, 1 },
{ 2, 2 },
{ 4, 3 },
{ 8, 4 }
};
row = rowLookup[rowCode()];
if (col == 0 || row == 0)
{
code = 0;
}
else
{
code = (byte)(col + (row - 1) * 4);
}
colCode = 0;
}
static void ADCToMotor(
ushort adc1,
ushort adc2,
// motor1 pins
FPGA.OutputSignal <bool> Motor1Enabled,
FPGA.OutputSignal <bool> Motor1Pin1,
FPGA.OutputSignal <bool> Motor1Pin2,
// motor2 pins
FPGA.OutputSignal <bool> Motor2Enabled,
FPGA.OutputSignal <bool> Motor2Pin1,
FPGA.OutputSignal <bool> Motor2Pin2,
FPGA.OutputSignal <bool> TXD
)
{
sbyte motor1 = 0, motor2 = -127;
ushort rpm = 0;
ushort currentRpm = 0;
// Peaks: 2150, 4300
FPGA.Collections.ReadOnlyDictionary <ushort, sbyte> motor1Map = new FPGA.Collections.ReadOnlyDictionary <ushort, sbyte>()
{
{ 0, -127 },
{ 500, -127 },
{ 1000, -127 },
{ 1500, -63 }, // 193
{ 2000, -12 },
{ 2500, 30 },
{ 3000, 85 },
{ 3500, 127 },
{ 4000, 127 },
{ 4500, 127 },
{ 5000, 127 },
{ 5500, 105 },
{ 6000, 34 },
};
FPGA.Collections.ReadOnlyDictionary <ushort, sbyte> motor2Map = new FPGA.Collections.ReadOnlyDictionary <ushort, sbyte>()
{
{ 0, 0 },
{ 500, -46 }, //210
{ 1000, -106 },
{ 1500, -127 },
{ 2000, -127 },
{ 2500, -127 }, // 128
{ 3000, -127 },
{ 3500, -81 }, // 175
{ 4000, -25 },
{ 4500, 25 },
{ 5000, 74 },
{ 5500, 127 },
{ 6000, 127 },
};
Action handler = () =>
{
//motor1 = 0;// -127;
//motor2 = -128;
//Controllers.TachoDriver.ToMotorValue(adc1, out motor1);
//Controllers.TachoDriver.ToMotorValue(adc2, out motor2);
while (currentRpm != rpm)
{
if (currentRpm > rpm)
{
currentRpm -= 500;
}
else if (currentRpm < rpm)
{
currentRpm += 500;
}
motor1 = motor1Map[currentRpm];
motor2 = motor2Map[currentRpm];
FPGA.Runtime.Delay(TimeSpan.FromMilliseconds(50));
}
};
Action rmpHandler = () =>
{
if (rpm == 6000)
{
rpm = 0;
}
else
{
rpm += 500;
}
};
FPGA.Config.OnTimer(TimeSpan.FromMilliseconds(100), handler);
FPGA.Config.OnTimer(TimeSpan.FromMilliseconds(1000), rmpHandler);
Drivers.L298.SingleMotorDriver(motor1, Motor1Pin1, Motor1Pin2, Motor1Enabled);
Drivers.L298.SingleMotorDriver(motor2, Motor2Pin1, Motor2Pin2, Motor2Enabled);
Controllers.TachoDriver.ReportTacho(motor1, motor2, TXD);
}
public static void Keccak1600(
FPGA.Register <ulong> a00, FPGA.Register <ulong> a01, FPGA.Register <ulong> a02, FPGA.Register <ulong> a03, FPGA.Register <ulong> a04,
FPGA.Register <ulong> a05, FPGA.Register <ulong> a06, FPGA.Register <ulong> a07, FPGA.Register <ulong> a08, FPGA.Register <ulong> a09,
FPGA.Register <ulong> a10, FPGA.Register <ulong> a11, FPGA.Register <ulong> a12, FPGA.Register <ulong> a13, FPGA.Register <ulong> a14,
FPGA.Register <ulong> a15, FPGA.Register <ulong> a16, FPGA.Register <ulong> a17, FPGA.Register <ulong> a18, FPGA.Register <ulong> a19,
FPGA.Register <ulong> a20, FPGA.Register <ulong> a21, FPGA.Register <ulong> a22, FPGA.Register <ulong> a23, FPGA.Register <ulong> a24
)
{
// TODO: check that map key is unsigned or allow key to be signed
FPGA.Collections.ReadOnlyDictionary <uint, ulong> constants = new FPGA.Collections.ReadOnlyDictionary <uint, ulong>()
{
{ 0, 0x0000000000000001 },
{ 1, 0x0000000000008082 },
{ 2, 0x800000000000808A },
{ 3, 0x8000000080008000 },
{ 4, 0x000000000000808B },
{ 5, 0x0000000080000001 },
{ 6, 0x8000000080008081 },
{ 7, 0x8000000000008009 },
{ 8, 0x000000000000008A },
{ 9, 0x0000000000000088 },
{ 10, 0x0000000080008009 },
{ 11, 0x000000008000000A },
{ 12, 0x000000008000808B },
{ 13, 0x800000000000008B },
{ 14, 0x8000000000008089 },
{ 15, 0x8000000000008003 },
{ 16, 0x8000000000008002 },
{ 17, 0x8000000000000080 },
{ 18, 0x000000000000800A },
{ 19, 0x800000008000000A },
{ 20, 0x8000000080008081 },
{ 21, 0x8000000000008080 },
{ 22, 0x0000000080000001 },
{ 23, 0x8000000080008008 },
};
ulong ulongMax = ulong.MaxValue;
for (uint round = 0; round < 24; round += 4)
{
ulong rc0, rc1, rc2, rc3;
rc0 = constants[round];
rc1 = constants[round + 1];
rc2 = constants[round + 2];
rc3 = constants[round + 3];
ulong t = 0, bc0 = 0, bc1 = 0, bc2 = 0, bc3 = 0, bc4 = 0, d0 = 0, d1 = 0, d2 = 0, d3 = 0, d4 = 0;
FPGA.Config.Suppress("W0003", t, bc0, bc1, bc2, bc3, bc4, d0, d1, d2, d3, d4);
FPGA.Signal <bool> round1Trigger = false, round2Trigger = false, round3Trigger = false, round4Trigger = false;
FPGA.Signal <bool> round1Completed = false, round2Completed = false, round3Completed = false, round4Completed = false;
Func <ulong> x0 = () => a00 ^ a05 ^ a10 ^ a15 ^ a20;
Func <ulong> x1 = () => a01 ^ a06 ^ a11 ^ a16 ^ a21;
Func <ulong> x2 = () => a02 ^ a07 ^ a12 ^ a17 ^ a22;
Func <ulong> x3 = () => a03 ^ a08 ^ a13 ^ a18 ^ a23;
Func <ulong> x4 = () => a04 ^ a09 ^ a14 ^ a19 ^ a24;
Func <ulong> xd0 = () => bc4 ^ (bc1 << 1 | bc1 >> 63);
Func <ulong> xd1 = () => bc0 ^ (bc2 << 1 | bc2 >> 63);
Func <ulong> xd2 = () => bc1 ^ (bc3 << 1 | bc3 >> 63);
Func <ulong> xd3 = () => bc2 ^ (bc4 << 1 | bc4 >> 63);
Func <ulong> xd4 = () => bc3 ^ (bc0 << 1 | bc0 >> 63);
Func <ulong> bc021 = () => bc0 ^ (bc2 & (bc1 ^ ulongMax));
Func <ulong> bc132 = () => bc1 ^ (bc3 & (bc2 ^ ulongMax));
Func <ulong> bc243 = () => bc2 ^ (bc4 & (bc3 ^ ulongMax));
Func <ulong> bc304 = () => bc3 ^ (bc0 & (bc4 ^ ulongMax));
Func <ulong> bc410 = () => bc4 ^ (bc1 & (bc0 ^ ulongMax));
Sequential round1 = () =>
{
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(x0, (v) => bc0 = v),
FPGA.Expressions.Assign(x1, (v) => bc1 = v),
FPGA.Expressions.Assign(x2, (v) => bc2 = v),
FPGA.Expressions.Assign(x3, (v) => bc3 = v),
FPGA.Expressions.Assign(x4, (v) => bc4 = v)
);
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(xd0, (v) => d0 = v),
FPGA.Expressions.Assign(xd1, (v) => d1 = v),
FPGA.Expressions.Assign(xd2, (v) => d2 = v),
FPGA.Expressions.Assign(xd3, (v) => d3 = v),
FPGA.Expressions.Assign(xd4, (v) => d4 = v)
);
bc0 = a00 ^ d0;
t = a06 ^ d1;
bc1 = FPGA.Runtime.Rol(44, t);
t = a12 ^ d2;
bc2 = FPGA.Runtime.Rol(43, t);
t = a18 ^ d3;
bc3 = FPGA.Runtime.Rol(21, t);
t = a24 ^ d4;
bc4 = FPGA.Runtime.Rol(14, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021() ^ rc0, a00),
FPGA.Expressions.AssignRegister(bc132(), a06),
FPGA.Expressions.AssignRegister(bc243(), a12),
FPGA.Expressions.AssignRegister(bc304(), a18),
FPGA.Expressions.AssignRegister(bc410(), a24)
);
t = a10 ^ d0;
bc2 = FPGA.Runtime.Rol(3, t);
t = a16 ^ d1;
bc3 = FPGA.Runtime.Rol(45, t);
t = a22 ^ d2;
bc4 = FPGA.Runtime.Rol(61, t);
t = a03 ^ d3;
bc0 = FPGA.Runtime.Rol(28, t);
t = a09 ^ d4;
bc1 = FPGA.Runtime.Rol(20, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a10),
FPGA.Expressions.AssignRegister(bc132(), a16),
FPGA.Expressions.AssignRegister(bc243(), a22),
FPGA.Expressions.AssignRegister(bc304(), a03),
FPGA.Expressions.AssignRegister(bc410(), a09)
);
t = a20 ^ d0;
bc4 = FPGA.Runtime.Rol(18, t);
t = a01 ^ d1;
bc0 = FPGA.Runtime.Rol(1, t);
t = a07 ^ d2;
bc1 = FPGA.Runtime.Rol(6, t);
t = a13 ^ d3;
bc2 = FPGA.Runtime.Rol(25, t);
t = a19 ^ d4;
bc3 = FPGA.Runtime.Rol(8, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a20),
FPGA.Expressions.AssignRegister(bc132(), a01),
FPGA.Expressions.AssignRegister(bc243(), a07),
FPGA.Expressions.AssignRegister(bc304(), a13),
FPGA.Expressions.AssignRegister(bc410(), a19)
);
t = a05 ^ d0;
bc1 = FPGA.Runtime.Rol(36, t);
t = a11 ^ d1;
bc2 = FPGA.Runtime.Rol(10, t);
t = a17 ^ d2;
bc3 = FPGA.Runtime.Rol(15, t);
t = a23 ^ d3;
bc4 = FPGA.Runtime.Rol(56, t);
t = a04 ^ d4;
bc0 = FPGA.Runtime.Rol(27, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a05),
FPGA.Expressions.AssignRegister(bc132(), a11),
FPGA.Expressions.AssignRegister(bc243(), a17),
FPGA.Expressions.AssignRegister(bc304(), a23),
FPGA.Expressions.AssignRegister(bc410(), a04)
);
t = a15 ^ d0;
bc3 = FPGA.Runtime.Rol(41, t);
t = a21 ^ d1;
bc4 = FPGA.Runtime.Rol(2, t);
t = a02 ^ d2;
bc0 = FPGA.Runtime.Rol(62, t);
t = a08 ^ d3;
bc1 = FPGA.Runtime.Rol(55, t);
t = a14 ^ d4;
bc2 = FPGA.Runtime.Rol(39, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a15),
FPGA.Expressions.AssignRegister(bc132(), a21),
FPGA.Expressions.AssignRegister(bc243(), a02),
FPGA.Expressions.AssignRegister(bc304(), a08),
FPGA.Expressions.AssignRegister(bc410(), a14)
);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round1Completed));
};
FPGA.Config.OnSignal(round1Trigger, round1);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round1Trigger));
FPGA.Runtime.WaitForAllConditions(round1Completed);
// Round 2
Sequential round2 = () =>
{
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(x0, (v) => bc0 = v),
FPGA.Expressions.Assign(x1, (v) => bc1 = v),
FPGA.Expressions.Assign(x2, (v) => bc2 = v),
FPGA.Expressions.Assign(x3, (v) => bc3 = v),
FPGA.Expressions.Assign(x4, (v) => bc4 = v)
);
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(xd0, (v) => d0 = v),
FPGA.Expressions.Assign(xd1, (v) => d1 = v),
FPGA.Expressions.Assign(xd2, (v) => d2 = v),
FPGA.Expressions.Assign(xd3, (v) => d3 = v),
FPGA.Expressions.Assign(xd4, (v) => d4 = v)
);
bc0 = a00 ^ d0;
t = a16 ^ d1;
bc1 = FPGA.Runtime.Rol(44, t);
t = a07 ^ d2;
bc2 = FPGA.Runtime.Rol(43, t);
t = a23 ^ d3;
bc3 = FPGA.Runtime.Rol(21, t);
t = a14 ^ d4;
bc4 = FPGA.Runtime.Rol(14, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021() ^ rc1, a00),
FPGA.Expressions.AssignRegister(bc132(), a16),
FPGA.Expressions.AssignRegister(bc243(), a07),
FPGA.Expressions.AssignRegister(bc304(), a23),
FPGA.Expressions.AssignRegister(bc410(), a14)
);
t = a20 ^ d0;
bc2 = FPGA.Runtime.Rol(3, t);
t = a11 ^ d1;
bc3 = FPGA.Runtime.Rol(45, t);
t = a02 ^ d2;
bc4 = FPGA.Runtime.Rol(61, t);
t = a18 ^ d3;
bc0 = FPGA.Runtime.Rol(28, t);
t = a09 ^ d4;
bc1 = FPGA.Runtime.Rol(20, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a20),
FPGA.Expressions.AssignRegister(bc132(), a11),
FPGA.Expressions.AssignRegister(bc243(), a02),
FPGA.Expressions.AssignRegister(bc304(), a18),
FPGA.Expressions.AssignRegister(bc410(), a09)
);
t = a15 ^ d0;
bc4 = FPGA.Runtime.Rol(18, t);
t = a06 ^ d1;
bc0 = FPGA.Runtime.Rol(1, t);
t = a22 ^ d2;
bc1 = FPGA.Runtime.Rol(6, t);
t = a13 ^ d3;
bc2 = FPGA.Runtime.Rol(25, t);
t = a04 ^ d4;
bc3 = FPGA.Runtime.Rol(8, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a15),
FPGA.Expressions.AssignRegister(bc132(), a06),
FPGA.Expressions.AssignRegister(bc243(), a22),
FPGA.Expressions.AssignRegister(bc304(), a13),
FPGA.Expressions.AssignRegister(bc410(), a04)
);
t = a10 ^ d0;
bc1 = FPGA.Runtime.Rol(36, t);
t = a01 ^ d1;
bc2 = FPGA.Runtime.Rol(10, t);
t = a17 ^ d2;
bc3 = FPGA.Runtime.Rol(15, t);
t = a08 ^ d3;
bc4 = FPGA.Runtime.Rol(56, t);
t = a24 ^ d4;
bc0 = FPGA.Runtime.Rol(27, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a10),
FPGA.Expressions.AssignRegister(bc132(), a01),
FPGA.Expressions.AssignRegister(bc243(), a17),
FPGA.Expressions.AssignRegister(bc304(), a08),
FPGA.Expressions.AssignRegister(bc410(), a24)
);
t = a05 ^ d0;
bc3 = FPGA.Runtime.Rol(41, t);
t = a21 ^ d1;
bc4 = FPGA.Runtime.Rol(2, t);
t = a12 ^ d2;
bc0 = FPGA.Runtime.Rol(62, t);
t = a03 ^ d3;
bc1 = FPGA.Runtime.Rol(55, t);
t = a19 ^ d4;
bc2 = FPGA.Runtime.Rol(39, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a05),
FPGA.Expressions.AssignRegister(bc132(), a21),
FPGA.Expressions.AssignRegister(bc243(), a12),
FPGA.Expressions.AssignRegister(bc304(), a03),
FPGA.Expressions.AssignRegister(bc410(), a19)
);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round2Completed));
};
FPGA.Config.OnSignal(round2Trigger, round2);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round2Trigger));
FPGA.Runtime.WaitForAllConditions(round2Completed);
// Round 3
Sequential round3 = () =>
{
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(x0, (v) => bc0 = v),
FPGA.Expressions.Assign(x1, (v) => bc1 = v),
FPGA.Expressions.Assign(x2, (v) => bc2 = v),
FPGA.Expressions.Assign(x3, (v) => bc3 = v),
FPGA.Expressions.Assign(x4, (v) => bc4 = v)
);
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(xd0, (v) => d0 = v),
FPGA.Expressions.Assign(xd1, (v) => d1 = v),
FPGA.Expressions.Assign(xd2, (v) => d2 = v),
FPGA.Expressions.Assign(xd3, (v) => d3 = v),
FPGA.Expressions.Assign(xd4, (v) => d4 = v)
);
bc0 = a00 ^ d0;
t = a11 ^ d1;
bc1 = FPGA.Runtime.Rol(44, t);
t = a22 ^ d2;
bc2 = FPGA.Runtime.Rol(43, t);
t = a08 ^ d3;
bc3 = FPGA.Runtime.Rol(21, t);
t = a19 ^ d4;
bc4 = FPGA.Runtime.Rol(14, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021() ^ rc2, a00),
FPGA.Expressions.AssignRegister(bc132(), a11),
FPGA.Expressions.AssignRegister(bc243(), a22),
FPGA.Expressions.AssignRegister(bc304(), a08),
FPGA.Expressions.AssignRegister(bc410(), a19)
);
t = a15 ^ d0;
bc2 = FPGA.Runtime.Rol(3, t);
t = a01 ^ d1;
bc3 = FPGA.Runtime.Rol(45, t);
t = a12 ^ d2;
bc4 = FPGA.Runtime.Rol(61, t);
t = a23 ^ d3;
bc0 = FPGA.Runtime.Rol(28, t);
t = a09 ^ d4;
bc1 = FPGA.Runtime.Rol(20, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a15),
FPGA.Expressions.AssignRegister(bc132(), a01),
FPGA.Expressions.AssignRegister(bc243(), a12),
FPGA.Expressions.AssignRegister(bc304(), a23),
FPGA.Expressions.AssignRegister(bc410(), a09)
);
t = a05 ^ d0;
bc4 = FPGA.Runtime.Rol(18, t);
t = a16 ^ d1;
bc0 = FPGA.Runtime.Rol(1, t);
t = a02 ^ d2;
bc1 = FPGA.Runtime.Rol(6, t);
t = a13 ^ d3;
bc2 = FPGA.Runtime.Rol(25, t);
t = a24 ^ d4;
bc3 = FPGA.Runtime.Rol(8, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a05),
FPGA.Expressions.AssignRegister(bc132(), a16),
FPGA.Expressions.AssignRegister(bc243(), a02),
FPGA.Expressions.AssignRegister(bc304(), a13),
FPGA.Expressions.AssignRegister(bc410(), a24)
);
t = a20 ^ d0;
bc1 = FPGA.Runtime.Rol(36, t);
t = a06 ^ d1;
bc2 = FPGA.Runtime.Rol(10, t);
t = a17 ^ d2;
bc3 = FPGA.Runtime.Rol(15, t);
t = a03 ^ d3;
bc4 = FPGA.Runtime.Rol(56, t);
t = a14 ^ d4;
bc0 = FPGA.Runtime.Rol(27, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a20),
FPGA.Expressions.AssignRegister(bc132(), a06),
FPGA.Expressions.AssignRegister(bc243(), a17),
FPGA.Expressions.AssignRegister(bc304(), a03),
FPGA.Expressions.AssignRegister(bc410(), a14)
);
t = a10 ^ d0;
bc3 = FPGA.Runtime.Rol(41, t);
t = a21 ^ d1;
bc4 = FPGA.Runtime.Rol(2, t);
t = a07 ^ d2;
bc0 = FPGA.Runtime.Rol(62, t);
t = a18 ^ d3;
bc1 = FPGA.Runtime.Rol(55, t);
t = a04 ^ d4;
bc2 = FPGA.Runtime.Rol(39, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a10),
FPGA.Expressions.AssignRegister(bc132(), a21),
FPGA.Expressions.AssignRegister(bc243(), a07),
FPGA.Expressions.AssignRegister(bc304(), a18),
FPGA.Expressions.AssignRegister(bc410(), a04)
);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round3Completed));
};
FPGA.Config.OnSignal(round3Trigger, round3);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round3Trigger));
FPGA.Runtime.WaitForAllConditions(round3Completed);
// Round 4
Sequential round4 = () =>
{
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(x0, (v) => bc0 = v),
FPGA.Expressions.Assign(x1, (v) => bc1 = v),
FPGA.Expressions.Assign(x2, (v) => bc2 = v),
FPGA.Expressions.Assign(x3, (v) => bc3 = v),
FPGA.Expressions.Assign(x4, (v) => bc4 = v)
);
FPGA.Runtime.Assign(
FPGA.Expressions.Assign(xd0, (v) => d0 = v),
FPGA.Expressions.Assign(xd1, (v) => d1 = v),
FPGA.Expressions.Assign(xd2, (v) => d2 = v),
FPGA.Expressions.Assign(xd3, (v) => d3 = v),
FPGA.Expressions.Assign(xd4, (v) => d4 = v)
);
bc0 = a00 ^ d0;
t = a01 ^ d1;
bc1 = FPGA.Runtime.Rol(44, t);
t = a02 ^ d2;
bc2 = FPGA.Runtime.Rol(43, t);
t = a03 ^ d3;
bc3 = FPGA.Runtime.Rol(21, t);
t = a04 ^ d4;
bc4 = FPGA.Runtime.Rol(14, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021() ^ rc3, a00),
FPGA.Expressions.AssignRegister(bc132(), a01),
FPGA.Expressions.AssignRegister(bc243(), a02),
FPGA.Expressions.AssignRegister(bc304(), a03),
FPGA.Expressions.AssignRegister(bc410(), a04)
);
t = a05 ^ d0;
bc2 = FPGA.Runtime.Rol(3, t);
t = a06 ^ d1;
bc3 = FPGA.Runtime.Rol(45, t);
t = a07 ^ d2;
bc4 = FPGA.Runtime.Rol(61, t);
t = a08 ^ d3;
bc0 = FPGA.Runtime.Rol(28, t);
t = a09 ^ d4;
bc1 = FPGA.Runtime.Rol(20, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a05),
FPGA.Expressions.AssignRegister(bc132(), a06),
FPGA.Expressions.AssignRegister(bc243(), a07),
FPGA.Expressions.AssignRegister(bc304(), a08),
FPGA.Expressions.AssignRegister(bc410(), a09)
);
t = a10 ^ d0;
bc4 = FPGA.Runtime.Rol(18, t);
t = a11 ^ d1;
bc0 = FPGA.Runtime.Rol(1, t);
t = a12 ^ d2;
bc1 = FPGA.Runtime.Rol(6, t);
t = a13 ^ d3;
bc2 = FPGA.Runtime.Rol(25, t);
t = a14 ^ d4;
bc3 = FPGA.Runtime.Rol(8, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a10),
FPGA.Expressions.AssignRegister(bc132(), a11),
FPGA.Expressions.AssignRegister(bc243(), a12),
FPGA.Expressions.AssignRegister(bc304(), a13),
FPGA.Expressions.AssignRegister(bc410(), a14)
);
t = a15 ^ d0;
bc1 = FPGA.Runtime.Rol(36, t);
t = a16 ^ d1;
bc2 = FPGA.Runtime.Rol(10, t);
t = a17 ^ d2;
bc3 = FPGA.Runtime.Rol(15, t);
t = a18 ^ d3;
bc4 = FPGA.Runtime.Rol(56, t);
t = a19 ^ d4;
bc0 = FPGA.Runtime.Rol(27, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a15),
FPGA.Expressions.AssignRegister(bc132(), a16),
FPGA.Expressions.AssignRegister(bc243(), a17),
FPGA.Expressions.AssignRegister(bc304(), a18),
FPGA.Expressions.AssignRegister(bc410(), a19)
);
t = a20 ^ d0;
bc3 = FPGA.Runtime.Rol(41, t);
t = a21 ^ d1;
bc4 = FPGA.Runtime.Rol(2, t);
t = a22 ^ d2;
bc0 = FPGA.Runtime.Rol(62, t);
t = a23 ^ d3;
bc1 = FPGA.Runtime.Rol(55, t);
t = a24 ^ d4;
bc2 = FPGA.Runtime.Rol(39, t);
FPGA.Runtime.Assign(
FPGA.Expressions.AssignRegister(bc021(), a20),
FPGA.Expressions.AssignRegister(bc132(), a21),
FPGA.Expressions.AssignRegister(bc243(), a22),
FPGA.Expressions.AssignRegister(bc304(), a23),
FPGA.Expressions.AssignRegister(bc410(), a24)
);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round4Completed));
};
FPGA.Config.OnSignal(round4Trigger, round4);
FPGA.Runtime.Assign(FPGA.Expressions.AssignSignal(true, round4Trigger));
FPGA.Runtime.WaitForAllConditions(round4Completed);
}
}
