public SystemControlUnit(VR4300 cpu)
{
this.cpu = cpu;
Config = new ConfigRegister(this);
Status = new StatusRegister(this);
Cause = new CauseRegister(this);
operations = new Dictionary <Instruction, Action <Instruction> >
{
[From(OpCode.MT)] = i =>
{
var destination = i.RD;
var data = cpu.GPR[i.RT];
switch ((RegisterIndex)destination)
{
case RegisterIndex.Cause:
Registers[destination] &= ~CauseRegister.WriteMask;
Registers[destination] |= data & CauseRegister.WriteMask;
return;
case RegisterIndex.Compare:
var ip = Cause.IP;
ip.TimerInterrupt = false;
Cause.IP = ip;
break;
}
Registers[destination] = data;
},
[From(OpCode.MF)] = i => cpu.GPR[i.RT] = (ulong)(int)Registers[i.RD],
[From(FunctOpCode.TLBWI)] = i => { /* TODO. */ },
[From(FunctOpCode.ERET)] = i =>
{
if (Status.ERL)
{
cpu.PC = Registers[(int)RegisterIndex.ErrorEPC];
Status.ERL = false;
}
else
{
cpu.PC = Registers[(int)RegisterIndex.EPC];
Status.EXL = false;
}
cpu.LLBit = false;
cpu.DelaySlot = null;
}
};
}
public void TestExceptionCode()
{
CauseRegister reg = new CauseRegister();
reg.ExcCode = 5;
Assert.Equal<ExceptionCode>(ExceptionCode.AddressErrorStore, reg.ExceptionType);
reg.ExceptionType = ExceptionCode.Watch;
Assert.Equal(23, reg.ExcCode);
reg.ExcCode = 5;
Assert.Equal(20U, reg.RegisterValue);
reg.ExceptionType = ExceptionCode.AddressErrorStore;
Assert.Equal(20U, reg.RegisterValue);
}
public CP0Registers()
{
m_Regs = new UInt64[32];
m_SR = new StatusRegister();
m_CauseReg = new CauseRegister();
}
