public Tesbernch_Multiplier() { _m_clk = new Clock(ClockPeriod) { Clk = _clk }; _m_signal = new XilinxMultiplier() { CLK = _clk, A = _A, B = _B, P = _P, }; _m_logger1 = new ConsoleLogger<StdLogicVector>() { DataIn = _A }; _m_logger2 = new ConsoleLogger<StdLogicVector>() { DataIn = _B }; _m_logger3 = new ConsoleLogger<StdLogicVector>() { DataIn = _P }; }
public IXILMapping TryMapOne(ITransactionSite taSite, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, bool swap) { var fu = taSite.Host; XilinxMultiplier mul = fu as XilinxMultiplier; if (mul == null) { return(null); } if (instr.Name != InstructionCodes.Mul) { return(null); } if (mul.MultType != XilinxMultiplier.EMultiplierType.ParallelMultiplier) { return(null); } FixFormat fmta, fmtb, fmtr; fmta = GetFixFormat(operandTypes[0]); fmtb = GetFixFormat(operandTypes[1]); fmtr = GetFixFormat(resultTypes[0]); if (fmta == null || fmtb == null || fmtr == null) { return(null); } bool expectSigned = fmta.IsSigned || fmtb.IsSigned; if (expectSigned != fmtr.IsSigned) { return(null); } int expectedHigh = fmtr.IntWidth + fmta.FracWidth + fmtb.FracWidth - 1; int expectedLow = fmta.FracWidth + fmtb.FracWidth - fmtr.FracWidth; if (fmta.TotalWidth != mul.PortAWidth || fmtb.TotalWidth != mul.PortBWidth || expectedHigh != mul.OutputWidthHigh || expectedLow != mul.OutputWidthLow) { return(null); } return(new XILMapping(mul, swap)); }
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj) { if (instr.Name != InstructionCodes.Mul) { return(null); } FixFormat fmta, fmtb, fmtr; fmta = GetFixFormat(operandTypes[0]); fmtb = GetFixFormat(operandTypes[1]); fmtr = GetFixFormat(resultTypes[0]); if (fmta == null || fmtb == null || fmtr == null) { return(null); } bool expectSigned = fmta.IsSigned || fmtb.IsSigned; if (expectSigned != fmtr.IsSigned) { return(null); } int high = fmtr.IntWidth + fmta.FracWidth + fmtb.FracWidth - 1; int low = fmta.FracWidth + fmtb.FracWidth - fmtr.FracWidth; var xproj = proj as XilinxProject; XilinxMultiplier.EGenerator gen = XilinxMultiplier.EGenerator.Multiplier_11_2; switch (xproj.ISEVersion) { case EISEVersion._11_1: case EISEVersion._11_2: case EISEVersion._11_3: case EISEVersion._11_4: case EISEVersion._11_5: gen = XilinxMultiplier.EGenerator.Multiplier_11_0; break; } XilinxMultiplier mul = new XilinxMultiplier() { Generator = gen, HasCE = false, MultiplierConstruction = XilinxMultiplier.EConstruction.UseMults, MultType = XilinxMultiplier.EMultiplierType.ParallelMultiplier, OptGoal = XilinxMultiplier.EOptimizationGoal.Speed, UseCustomOutputWidth = true, OutputWidthHigh = high, OutputWidthLow = low, PortAType = fmta.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortAWidth = fmta.TotalWidth, PortBType = fmtb.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortBWidth = fmtb.TotalWidth, HasSCLR = false, UseRounding = false, ZeroDetect = false }; int optStages = ComputeOptimalPipeStages(mul); { // debug only DesignContext.Push(); var mul2 = new XilinxMultiplier() { Generator = gen, HasCE = false, MultiplierConstruction = XilinxMultiplier.EConstruction.UseMults, MultType = XilinxMultiplier.EMultiplierType.ParallelMultiplier, OptGoal = XilinxMultiplier.EOptimizationGoal.Speed, UseCustomOutputWidth = true, OutputWidthHigh = high, OutputWidthLow = low, PortAType = fmtb.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortAWidth = fmtb.TotalWidth, PortBType = fmta.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortBWidth = fmta.TotalWidth, HasSCLR = false, UseRounding = false, ZeroDetect = false }; Debug.Assert(optStages == ComputeOptimalPipeStages(mul2)); DesignContext.Pop(); } int scaledStages = (int)Math.Round(Config.PipeStageScaling * optStages); mul.PipeStages = scaledStages; return(new XILMapping(mul, false)); }
private int ComputeOptimalPipeStages(XilinxMultiplier mul) { // Assumption: Virtex6 device if (mul.PortAWidth <= 9 && mul.PortBWidth <= 9 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(3); } if (mul.PortAWidth <= 9 && mul.PortBWidth <= 9 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(4); } if (mul.PortAWidth <= 12 && mul.PortBWidth <= 12 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(3); } if (mul.PortAWidth <= 12 && mul.PortBWidth <= 12 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(4); } if (mul.PortAWidth <= 18 && mul.PortBWidth <= 18 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Signed) { return(3); } if (mul.PortAWidth <= 20 && mul.PortBWidth <= 20 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Signed) { return(4); } if (mul.PortAWidth <= 20 && mul.PortBWidth <= 20 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Signed) { return(3); } if (mul.PortAWidth <= 24 && mul.PortBWidth <= 24 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(4); } if (mul.PortAWidth <= 24 && mul.PortBWidth <= 24 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(5); } if (mul.PortAWidth <= 25 && mul.PortBWidth <= 18 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.ResultType == XilinxMultiplier.ESignedness.Signed) { return(3); } if (mul.PortAWidth <= 18 && mul.PortBWidth <= 25 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.ResultType == XilinxMultiplier.ESignedness.Signed) { return(3); } if (mul.PortAWidth <= 35 && mul.PortBWidth <= 35 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Signed) { return(6); } if (mul.PortAWidth <= 53 && mul.PortBWidth <= 53 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) { return(12); } // don't know... return(12); }
public XILMapping(XilinxMultiplier host, bool swap) { _host = host; _swap = swap; }
public TransactionSite(XilinxMultiplier host) : base(host) { _host = host; }
public IXILMapping TryAllocate(Component host, XILInstr instr, TypeDescriptor[] operandTypes, TypeDescriptor[] resultTypes, IProject proj) { if (instr.Name != InstructionCodes.Mul) return null; FixFormat fmta, fmtb, fmtr; fmta = GetFixFormat(operandTypes[0]); fmtb = GetFixFormat(operandTypes[1]); fmtr = GetFixFormat(resultTypes[0]); if (fmta == null || fmtb == null || fmtr == null) return null; bool expectSigned = fmta.IsSigned || fmtb.IsSigned; if (expectSigned != fmtr.IsSigned) return null; int high = fmtr.IntWidth + fmta.FracWidth + fmtb.FracWidth - 1; int low = fmta.FracWidth + fmtb.FracWidth - fmtr.FracWidth; var xproj = proj as XilinxProject; XilinxMultiplier.EGenerator gen = XilinxMultiplier.EGenerator.Multiplier_11_2; switch (xproj.ISEVersion) { case EISEVersion._11_1: case EISEVersion._11_2: case EISEVersion._11_3: case EISEVersion._11_4: case EISEVersion._11_5: gen = XilinxMultiplier.EGenerator.Multiplier_11_0; break; } XilinxMultiplier mul = new XilinxMultiplier() { Generator = gen, HasCE = false, MultiplierConstruction = XilinxMultiplier.EConstruction.UseMults, MultType = XilinxMultiplier.EMultiplierType.ParallelMultiplier, OptGoal = XilinxMultiplier.EOptimizationGoal.Speed, UseCustomOutputWidth = true, OutputWidthHigh = high, OutputWidthLow = low, PortAType = fmta.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortAWidth = fmta.TotalWidth, PortBType = fmtb.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortBWidth = fmtb.TotalWidth, HasSCLR = false, UseRounding = false, ZeroDetect = false }; int optStages = ComputeOptimalPipeStages(mul); { // debug only DesignContext.Push(); var mul2 = new XilinxMultiplier() { Generator = gen, HasCE = false, MultiplierConstruction = XilinxMultiplier.EConstruction.UseMults, MultType = XilinxMultiplier.EMultiplierType.ParallelMultiplier, OptGoal = XilinxMultiplier.EOptimizationGoal.Speed, UseCustomOutputWidth = true, OutputWidthHigh = high, OutputWidthLow = low, PortAType = fmtb.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortAWidth = fmtb.TotalWidth, PortBType = fmta.IsSigned ? XilinxMultiplier.ESignedness.Signed : XilinxMultiplier.ESignedness.Unsigned, PortBWidth = fmta.TotalWidth, HasSCLR = false, UseRounding = false, ZeroDetect = false }; Debug.Assert(optStages == ComputeOptimalPipeStages(mul2)); DesignContext.Pop(); } int scaledStages = (int)Math.Round(Config.PipeStageScaling * optStages); mul.PipeStages = scaledStages; return new XILMapping(mul, false); }
private int ComputeOptimalPipeStages(XilinxMultiplier mul) { // Assumption: Virtex6 device if (mul.PortAWidth <= 9 && mul.PortBWidth <= 9 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 3; if (mul.PortAWidth <= 9 && mul.PortBWidth <= 9 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 4; if (mul.PortAWidth <= 12 && mul.PortBWidth <= 12 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 3; if (mul.PortAWidth <= 12 && mul.PortBWidth <= 12 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseLuts && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 4; if (mul.PortAWidth <= 18 && mul.PortBWidth <= 18 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Signed) return 3; if (mul.PortAWidth <= 20 && mul.PortBWidth <= 20 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Signed) return 4; if (mul.PortAWidth <= 20 && mul.PortBWidth <= 20 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Signed) return 3; if (mul.PortAWidth <= 24 && mul.PortBWidth <= 24 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 4; if (mul.PortAWidth <= 24 && mul.PortBWidth <= 24 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Area && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 5; if (mul.PortAWidth <= 25 && mul.PortBWidth <= 18 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.ResultType == XilinxMultiplier.ESignedness.Signed) return 3; if (mul.PortAWidth <= 18 && mul.PortBWidth <= 25 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.ResultType == XilinxMultiplier.ESignedness.Signed) return 3; if (mul.PortAWidth <= 35 && mul.PortBWidth <= 35 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Signed) return 6; if (mul.PortAWidth <= 53 && mul.PortBWidth <= 53 && mul.MultiplierConstruction == XilinxMultiplier.EConstruction.UseMults && mul.OptGoal == XilinxMultiplier.EOptimizationGoal.Speed && mul.ResultType == XilinxMultiplier.ESignedness.Unsigned) return 12; // don't know... return 12; }