private string SignalRegion(RenderStateProcess renderer, int indentation) { var memsize = m_memory.Length * DataWidthA; var config = new BlockRamConfig(renderer, DataWidthA, memsize, true); var self = renderer.Process; var outbusa = self.OutputBusses.First(x => typeof(IOutputA).IsAssignableFrom(x.SourceInstance.BusType)); var outbusb = self.OutputBusses.First(x => typeof(IOutputB).IsAssignableFrom(x.SourceInstance.BusType)); var inbusa = self.InputBusses.First(x => typeof(IInputA).IsAssignableFrom(x.SourceInstance.BusType)); var inbusb = self.InputBusses.First(x => typeof(IInputB).IsAssignableFrom(x.SourceInstance.BusType)); string template; if (typeof(TAddress) == typeof(int)) { template = $@" signal ENA_internal: std_logic; signal WEA_internal: std_logic_vector({config.wewidth - 1} downto 0); signal DIA_internal : std_logic_vector({DataWidthA - 1} downto 0); signal DOA_internal : std_logic_vector({DataWidthA - 1} downto 0); signal ADDRA_internal_partial : std_logic_vector({config.realaddrwidth - 1} downto 0); signal ADDRA_internal : std_logic_vector(31 downto 0); signal ENB_internal: std_logic; signal WEB_internal: std_logic_vector({config.wewidth - 1} downto 0); signal DIB_internal : std_logic_vector({DataWidthB - 1} downto 0); signal DOB_internal : std_logic_vector({DataWidthB - 1} downto 0); signal ADDRB_internal_partial : std_logic_vector({config.realaddrwidth - 1} downto 0); signal ADDRB_internal : std_logic_vector(31 downto 0); "; } else { template = $@" signal ENA_internal: std_logic; signal WEA_internal: std_logic_vector({config.wewidth - 1} downto 0); signal DIA_internal : std_logic_vector({DataWidthA - 1} downto 0); signal DOA_internal : std_logic_vector({DataWidthA - 1} downto 0); signal ADDRA_internal : std_logic_vector({config.realaddrwidth - 1} downto 0); signal ENB_internal: std_logic; signal WEB_internal: std_logic_vector({config.wewidth - 1} downto 0); signal DIB_internal : std_logic_vector({DataWidthB - 1} downto 0); signal DOB_internal : std_logic_vector({DataWidthB - 1} downto 0); signal ADDRB_internal : std_logic_vector({config.realaddrwidth - 1} downto 0); "; } return(VHDLHelper.ReIndentTemplate(template, indentation)); }
/// <summary> /// Creates the signal region /// </summary> /// <returns>The signal region.</returns> /// <param name="renderer">The renderer instance.</param> /// <param name="indentation">The current indentation.</param> private string SignalRegion(RenderStateProcess renderer, int indentation) { var self = renderer.Process; var outbus = self.OutputBusses.First(); var inreadbus = self.InputBusses.First(x => typeof(IReadIn).IsAssignableFrom(x.SourceInstance.BusType)); var inwritebus = self.InputBusses.First(x => typeof(IWriteIn).IsAssignableFrom(x.SourceInstance.BusType)); var memsize = m_memory.Length * DataWidth; var config = new BlockRamConfig(renderer, DataWidth, memsize, false); var rdaddr_partial = string.Empty; var wraddr_partial = string.Empty; string template; if (typeof(TAddress) == typeof(int)) { template = $@" signal RDEN_internal: std_logic; signal WREN_internal: std_logic; signal DI_internal : std_logic_vector({DataWidth - 1} downto 0); signal DO_internal : std_logic_vector({DataWidth - 1} downto 0); signal RDADDR_internal_partial : std_logic_vector({config.realaddrwidth - 1} downto 0); signal WRADDR_internal_partial : std_logic_vector({config.realaddrwidth - 1} downto 0); signal RDADDR_internal : std_logic_vector(31 downto 0); signal WRADDR_internal : std_logic_vector(31 downto 0); "; } else { template = $@" signal RDEN_internal: std_logic; signal WREN_internal: std_logic; signal DI_internal : std_logic_vector({DataWidth - 1} downto 0); signal DO_internal : std_logic_vector({DataWidth - 1} downto 0); signal RDADDR_internal : std_logic_vector({config.realaddrwidth - 1} downto 0); signal WRADDR_internal : std_logic_vector({config.realaddrwidth - 1} downto 0); "; } return(VHDLHelper.ReIndentTemplate(template, indentation)); }
private string ProcessRegion(RenderStateProcess renderer, int indentation) { var memsize = m_memory.Length * DataWidthA; var config = new BlockRamConfig(renderer, DataWidthA, memsize, true); var initlines = VHDLHelper.SplitDataBitStringToMemInit( VHDLHelper.GetDataBitStrings(m_initial), config.datawidth, config.paritybits ); var memlines = string.Join( "," + Environment.NewLine, Enumerable.Range(0, int.MaxValue) .Zip( initlines.Item1, (a, b) => string.Format(" INIT_{0:X2} => X\"{1}\"", a, b) ) ); var paritylines = string.Join( "," + Environment.NewLine, Enumerable.Range(0, int.MaxValue) .Zip( initlines.Item2, (a, b) => string.Format(" INITP_{0:X2} => X\"{1}\"", a, b) ) ); var initialvalue = VHDLHelper.GetDataBitString(m_resetinitial, DataWidthA); var self = renderer.Process; var outbusa = self.OutputBusses.First(x => typeof(IOutputA).IsAssignableFrom(x.SourceInstance.BusType)); var outbusb = self.OutputBusses.First(x => typeof(IOutputB).IsAssignableFrom(x.SourceInstance.BusType)); var inbusa = self.InputBusses.First(x => typeof(IInputA).IsAssignableFrom(x.SourceInstance.BusType)); var inbusb = self.InputBusses.First(x => typeof(IInputB).IsAssignableFrom(x.SourceInstance.BusType)); var addrpadding = AddressWidthA < config.realaddrwidth ? string.Empty : string.Format("\"{0}\" & ", new string('0', (config.realaddrwidth - AddressWidthA))); var partialaddrsuffix = typeof(TAddress) == typeof(int) ? "_partial" : string.Empty; var template = $@" {self.InstanceName}_inst : BRAM_TDP_MACRO generic map ( BRAM_SIZE => ""{(config.use36k ? "36Kb" : "18Kb")}"", -- Target BRAM, ""18Kb"" or ""36Kb"" DEVICE => ""{ config.targetdevice }"", --Target device: ""VIRTEX5"", ""VIRTEX6"", ""7SERIES"", ""SPARTAN6"" DOA_REG => 0, --Optional port A output register(0 or 1) DOB_REG => 0, --Optional port B output register(0 or 1) INIT_FILE => ""NONE"", READ_WIDTH_A => { DataWidthA }, -- Valid values are 1 - 36(19 - 36 only valid when BRAM_SIZE = ""36Kb"") READ_WIDTH_B => { DataWidthA }, -- Valid values are 1 - 36(19 - 36 only valid when BRAM_SIZE = ""36Kb"") SIM_COLLISION_CHECK => ""GENERATE_X_ONLY"", --Collision check enable ""ALL"", ""WARNING_ONLY"", --""GENERATE_X_ONLY"" or ""NONE"" SRVAL_A => X""{ initialvalue}"", --Set / Reset value for A port output SRVAL_B => X""{ initialvalue}"", --Set / Reset value for B port output WRITE_MODE_A => ""READ_FIRST"", -- ""WRITE_FIRST"", ""READ_FIRST"" or ""NO_CHANGE"" WRITE_MODE_B => ""READ_FIRST"", -- ""WRITE_FIRST"", ""READ_FIRST"" or ""NO_CHANGE"" WRITE_WIDTH_A => { DataWidthA }, -- Valid values are 1 - 36(19 - 36 only valid when BRAM_SIZE = ""36Kb"") WRITE_WIDTH_B => { DataWidthA }, -- Valid values are 1 - 36(19 - 36 only valid when BRAM_SIZE = ""36Kb"") -- The following INIT_xx declarations specify the initial contents of the RAM { memlines }, -- The next set of INITP_xx are for the parity bits { paritylines }, INIT_A => X""{ initialvalue}"", --Initial values on A output port INIT_B => X""{ initialvalue}"" --Initial values on B output port ) port map ( DOA => DOA_internal, -- Output port-A, width defined by READ_WIDTH_A parameter DOB => DOB_internal, -- Output port-B, width defined by READ_WIDTH_B parameter ADDRA => ADDRA_internal{partialaddrsuffix}, -- Input port-A address, width defined by Port A depth ADDRB => ADDRB_internal{partialaddrsuffix}, -- Input port-B address, width defined by Port B depth CLKA => CLK, -- 1-bit input port-A clock CLKB => CLK, -- 1-bit input port-B clock DIA => DIA_internal, -- Input port-A data, width defined by WRITE_WIDTH_A parameter DIB => DIB_internal, -- Input port-B data, width defined by WRITE_WIDTH_B parameter ENA => ENA_internal, -- 1-bit input port-A enable ENB => ENB_internal, -- 1-bit input port-B enable REGCEA => '0', -- 1-bit input port-A register enable REGCEB => '0', -- 1-bit input port-B register enable RSTA => RST, -- 1-bit input port-A reset RSTB => RST, -- 1-bit input port-B reset WEA => WEA_internal, -- Input port-A write enable, width defined by port A depth WEB => WEB_internal -- Input port-B write enable, width defined by port B depth ); -- End of BRAM_TDP_MACRO_inst instantiation {self.InstanceName}_Helper: process(RST,CLK, RDY) begin if RST = '1' then FIN <= '0'; elsif rising_edge(CLK) then FIN <= not RDY; end if; end process; ENA_internal <= ENB and {Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusa, self) + "_" + nameof(IInputA.Enabled)) }; WEA_internal <= (others => ENA_internal and {Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusa, self) + "_" + nameof(IInputA.IsWriting)) }); ADDRA_internal <= { addrpadding }std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusa, self) + "_" + nameof(IInputA.Address)) }); DIA_internal <= std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusa, self) + "_" + nameof(IInputA.Data)) }); { Naming.ToValidName(renderer.Parent.GetLocalBusName(outbusa, self) + "_" + nameof(IOutputA.Data)) } <= {renderer.Parent.VHDLWrappedTypeName(outbusa.Signals.First())}(DOA_internal); ENB_internal <= ENB and {Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusb, self) + "_" + nameof(IInputB.Enabled)) }; WEB_internal <= (others => ENB_internal and {Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusb, self) + "_" + nameof(IInputB.IsWriting)) }); ADDRB_internal <= { addrpadding }std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusb, self) + "_" + nameof(IInputB.Address)) }); DIB_internal <= std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inbusb, self) + "_" + nameof(IInputB.Data)) }); { Naming.ToValidName(renderer.Parent.GetLocalBusName(outbusb, self) + "_" + nameof(IOutputB.Data)) } <= {renderer.Parent.VHDLWrappedTypeName(outbusa.Signals.First())}(DOB_internal); "; if (partialaddrsuffix != string.Empty) { template += $@" ADDRA_internal_partial <= ADDRA_internal({config.realaddrwidth} downto 0); ADDRB_internal_partial <= ADDRB_internal({config.realaddrwidth} downto 0); "; } return(VHDLHelper.ReIndentTemplate(template, indentation)); }
/// <summary> /// Creates the process region /// </summary> /// <returns>The process region.</returns> /// <param name="renderer">The renderer instance.</param> /// <param name="indentation">The current indentation.</param> private string ProcessRegion(RenderStateProcess renderer, int indentation) { var memsize = m_memory.Length * DataWidth; var config = new BlockRamConfig(renderer, DataWidth, memsize, false); var initlines = VHDLHelper.SplitDataBitStringToMemInit( VHDLHelper.GetDataBitStrings(m_initial), config.datawidth, config.paritybits ); var memlines = string.Join( "," + Environment.NewLine, Enumerable.Range(0, int.MaxValue) .Zip( initlines.Item1, (a, b) => string.Format(" INIT_{0:X2} => X\"{1}\"", a, b) ) ); var paritylines = string.Join( "," + Environment.NewLine, Enumerable.Range(0, int.MaxValue) .Zip( initlines.Item2, (a, b) => string.Format(" INITP_{0:X2} => X\"{1}\"", a, b) ) ); var initialvalue = VHDLHelper.GetDataBitString(m_resetinitial, DataWidth); var self = renderer.Process; var outbus = self.OutputBusses.First(); var inreadbus = self.InputBusses.First(x => typeof(IReadIn).IsAssignableFrom(x.SourceInstance.BusType)); var inwritebus = self.InputBusses.First(x => typeof(IWriteIn).IsAssignableFrom(x.SourceInstance.BusType)); // Apparently, it does not work to do "(others => '1')" var westring = new string('1', config.wewidth); var addrpadding = AddressWidth <= config.realaddrwidth ? string.Empty : string.Format("\"{0}\" & ", new string('0', (config.realaddrwidth - AddressWidth))); var partialaddrsuffix = typeof(TAddress) == typeof(int) ? "_partial" : string.Empty; var template = $@" {self.InstanceName}_inst : BRAM_SDP_MACRO generic map ( BRAM_SIZE => ""{(config.use36k ? "36Kb" : "18Kb")}"", -- Target BRAM, ""18Kb"" or ""36Kb"" DEVICE => ""{ config.targetdevice }"", --Target device: ""VIRTEX5"", ""VIRTEX6"", ""7SERIES"", ""SPARTAN6"" WRITE_WIDTH => { DataWidth }, --Valid values are 1 - 72(37 - 72 only valid when BRAM_SIZE = ""36Kb"") READ_WIDTH => { DataWidth }, --Valid values are 1 - 72(37 - 72 only valid when BRAM_SIZE = ""36Kb"") DO_REG => 0, --Optional output register(0 or 1) INIT_FILE => ""NONE"", SIM_COLLISION_CHECK => ""GENERATE_X_ONLY"", --Collision check enable ""ALL"", ""WARNING_ONLY"", --""GENERATE_X_ONLY"" or ""NONE"" SRVAL => X""{ initialvalue}"", --Set / Reset value for port output WRITE_MODE => ""READ_FIRST"", --Specify ""READ_FIRST"" for same clock or synchronous clocks -- Specify ""WRITE_FIRST"" for asynchrononous clocks on ports -- The following INIT_xx declarations specify the initial contents of the RAM { memlines }, -- The next set of INITP_xx are for the parity bits { paritylines }, INIT => X""{ initialvalue}"" --Initial values on output port ) port map ( DO => DO_internal, -- Output read data port, width defined by READ_WIDTH parameter DI => DI_internal, -- Input write data port, width defined by WRITE_WIDTH parameter RDADDR => RDADDR_internal{partialaddrsuffix}, -- Input read address, width defined by read port depth RDCLK => CLK, -- 1-bit input read clock RDEN => RDEN_internal, -- 1-bit input read port enable REGCE => '0', -- 1-bit input read output register enable RST => RST, -- 1-bit input reset WE => ""{ westring }"", -- Input write enable, width defined by write port depth WRADDR => WRADDR_internal{partialaddrsuffix}, -- Input write address, width defined by write port depth WRCLK => CLK, -- 1-bit input write clock WREN => WREN_internal -- 1-bit input write port enable ); -- End of BRAM_SDP_MACRO_inst instantiation {self.InstanceName}_Helper: process(RST,CLK, RDY) begin if RST = '1' then FIN <= '0'; elsif rising_edge(CLK) then FIN <= not RDY; end if; end process; RDEN_internal <= ENB and {Naming.ToValidName(renderer.Parent.GetLocalBusName(inreadbus, self) + "_" + nameof(IReadIn.Enabled)) }; RDADDR_internal <= { addrpadding }std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inreadbus, self) + "_" + nameof(IReadIn.Address)) }); { Naming.ToValidName(renderer.Parent.GetLocalBusName(outbus, self) + "+" + nameof(IReadOut.Data)) } <= {renderer.Parent.VHDLWrappedTypeName(outbus.Signals.First())}(DO_internal); WREN_internal <= ENB and {Naming.ToValidName(renderer.Parent.GetLocalBusName(inwritebus, self) + "_" + nameof(IWriteIn.Enabled)) }; WRADDR_internal <= { addrpadding }std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inwritebus, self) + "_" + nameof(IWriteIn.Address)) }); DI_internal <= std_logic_vector({ Naming.ToValidName(renderer.Parent.GetLocalBusName(inwritebus, self) + "_" + nameof(IWriteIn.Data)) }); "; if (partialaddrsuffix != string.Empty) { template += $@" RDADDR_internal_partial <= RDADDR_internal({config.realaddrwidth} downto 0); WRADDR_internal_partial <= WRADDR_internal({config.realaddrwidth} downto 0); "; } return(VHDLHelper.ReIndentTemplate(template, indentation)); }