new public void enqueue_req(Req req) { //check if writeback hit List <Req> q = get_q(req); MemAddr addr = req.addr; if ((req.type == ReqType.RD) && (req.callback != null)) { List <Req> wq = writeqs[addr.rid, addr.bid]; int idx = wq.FindIndex(delegate(Req w) { return(w.block_addr == req.block_addr); }); if (idx != -1) { //writeback hit Sim.xbar.enqueue(req); Stat.procs[req.pid].wb_hit.Collect(); if ((!req.migrated_request) && (Config.proc.cache_insertion_policy == "PFA")) { Measurement.mem_num_dec(req);; // Measurement.DramCoreReqNumDec (req); } return; } } //writeback dumpster if (req.type == ReqType.WR && Config.mctrl.wb_dump) { req.addr.rowid = 0; } //enqueue proper Dbg.Assert(q.Count < q.Capacity); __enqueue_req(req, q); }
new public void __dequeue_req(Req req) { req.ts_departure = cycles; Dbg.Assert(req.ts_departure - req.ts_arrival > 0); if ((!req.migrated_request) && (Config.proc.cache_insertion_policy == "PFA")) { RowStat.UpdateMLP(RowStat.DramDict, req); Measurement.mem_num_dec(req); // Measurement.DramServiceTimeUpdate (req); // Measurement.DramCoreReqNumDec (req); } if (Config.proc.cache_insertion_policy == "PFA") { Measurement.DramCoreReqNumDec(req); } /* if (Config.proc.cache_insertion_policy == "RBLAMLP" || Config.proc.cache_insertion_policy == "PFA") * Measurement.DramSetCorePrevRowid (req); */ //sched meta_mctrl.dequeue_req(req); //load stat management if (!req.migrated_request) { if (req.type == ReqType.RD) { rload--; rload_per_proc[req.pid]--; rload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid]--; Dbg.Assert(rload >= 0); Dbg.Assert(rload_per_proc[req.pid] >= 0); Dbg.Assert(rload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid] >= 0); } else { wload--; wload_per_proc[req.pid]--; wload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid]--; Dbg.Assert(wload >= 0); Dbg.Assert(wload_per_proc[req.pid] >= 0); Dbg.Assert(wload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid] >= 0); // RequestPool.CacheWrite--; } } else { if (req.type == ReqType.RD) { rload--; } else { wload--; } } /* //dequeue proper * if (req.type == ReqType.RD) { * //traverse crossbar * //Sim.xbar.enqueue(req); * * Callback cb = req.cache_callback; * cb(req); * * * } * else { * bool removeok = mctrl_writeq.Remove(req); * Dbg.Assert(removeok); * req.latency = (int)(req.ts_departure - req.ts_arrival); * * Callback cb = req.cache_callback; * cb(req); * * * RequestPool.enpool(req); * }*/ //yang: //dequeue proper if (req.type == ReqType.RD) { Callback cb = req.cache_callback; cb(req); } else { bool removeok = mctrl_writeq.Remove(req); Dbg.Assert(removeok); req.latency = (int)(req.ts_departure - req.ts_arrival); Callback cb = req.cache_callback; cb(req); /* Callback cb1 = req.callback; * if (cb1!=null) * { * Console.WriteLine("Position3"); * RequestPool.CacheWrite--; * }*/ } }
public void __dequeue_req(Req req) { req.ts_departure = cycles; Dbg.Assert(req.ts_departure - req.ts_arrival > 0); if (!req.migrated_request) { if (Config.proc.cache_insertion_policy == "PFA") { RowStat.UpdateMLP(RowStat.NVMDict, req); Measurement.mem_num_dec(req); // Measurement.NVMServiceTimeUpdate (req); // Measurement.NVMCoreReqNumDec (req); Row_Migration_Policies.target = true; Row_Migration_Policies.target_req = req; } else if (Config.proc.cache_insertion_policy == "RBLA") { Row_Migration_Policies.target = true; Row_Migration_Policies.target_req = req; } } if (Config.proc.cache_insertion_policy == "PFA") { Measurement.NVMCoreReqNumDec(req); } /* if (Config.proc.cache_insertion_policy == "PFA") * { * Measurement.NVMSetCorePrevRowid (req); * } */ //sched meta_mctrl.dequeue_req(req); //load stat management if (!req.cache_wb) { if (req.type == ReqType.RD) { rload--; rload_per_proc[req.pid]--; rload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid]--; Dbg.Assert(rload >= 0); Dbg.Assert(rload_per_proc[req.pid] >= 0); Dbg.Assert(rload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid] >= 0); } else { wload--; wload_per_proc[req.pid]--; wload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid]--; Dbg.Assert(wload >= 0); Dbg.Assert(wload_per_proc[req.pid] >= 0); Dbg.Assert(wload_per_procrankbank[req.pid, req.addr.rid, req.addr.bid] >= 0); } } else { if (req.type == ReqType.RD) { rload--; } else { wload--; } } /* //dequeue proper * if (req.type == ReqType.RD) { * //traverse crossbar * Sim.xbar.enqueue(req); * * //cache * Sim.caches[Sim.get_cache(req.pid)].meta_insert(req); * } * else { * bool removeok = mctrl_writeq.Remove(req); * Dbg.Assert(removeok); * req.latency = (int)(req.ts_departure - req.ts_arrival); * * Callback cb = req.callback; * cb(req); * * if (!req.cache_wb) { * //cache * switch (Config.proc.cache_write_policy) { * case "WriteThrough": * // do nothing * break; * case "WriteBack": * Sim.caches[Sim.get_cache(req.pid)].meta_insert(req); * break; * } * } * else * RequestPool.enpool(req); * } */ if (req.type == ReqType.RD) { if (!Sim.caches[Sim.get_cache(req.pid)].is_cached(req)) { Sim.caches[Sim.get_cache(req.pid)].meta_insert(req); } // if (req.callback != null) Sim.xbar.enqueue(req); // else // RequestPool.enpool(req); } else { bool removeok = mctrl_writeq.Remove(req); Dbg.Assert(removeok); req.latency = (int)(req.ts_departure - req.ts_arrival); Callback cb = req.callback; if (!req.cache_wb) { switch (Config.proc.cache_write_policy) { case "WriteThrough": break; case "WriteBack": if (!Sim.caches[Sim.get_cache(req.pid)].is_cached(req)) { Sim.caches[Sim.get_cache(req.pid)].meta_insert(req); } break; } if (cb != null) { cb(req); } // else // RequestPool.enpool(req); } else { RequestPool.enpool(req); } } }