Copyright (C) 2019 John Devore
Copyright (C) 2019 Chance Henney, Juwan Moore, William Van Cleve
Copyright (C) 2017 Matthew Segraves, Zachary Terwort, Zachary Clear
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details: http://www.gnu.org/licenses/
Visiboole is a simulator of a Hardware Description Language(HDL) of the same name derived from Verilog, an HDL itself - IEEE standard 1800-2017. Its primary function is to create models of digital circuits that display a text representation of components. With the value of each component updated in real time, Visiboole is designed for use as a teaching aid that allows you to test programs without the need for physical hardware.
Released as a standalone executable file, Visiboole requires no drivers or runtime environment updates. Changing working modes runs the program you are editing or returns you to the editing window when you stop the program. Similar to traditional IDEs Visiboole code can be saved to a file that can be later be opened, modified, or distributed. Visiboole files can be edited and saved in other text editors, but can only be executed by a running instance of Visiboole.
Among many others, Visiboole supports the following:
- Traditional logic gates: AND, OR, XOR, etc
- Use of constants, variables, and arithmetic
- Advancing a program through a clock cycle
- Language to create, manipulate, and compare multiple variables at once
- Operating in base 2, 10, or 16
- Commenting and lax spacing