public override void DrawTiles(bool addIncrementForSelectedTiles, bool addIncrementForUserSelectedTiles) { int x = FPGA.FPGA.Instance.MaxX; int y = FPGA.FPGA.Instance.MaxY; // add 1 due to zero based indeces TileBitmap = new Bitmap((x + 1) * m_view.TileSize, (y + 1) * m_view.TileSize, m_pixelFormat); Graphics graphicsObj = Graphics.FromImage(TileBitmap); graphicsObj.Clear(Color.Gray); foreach (Tile tile in GetAllTiles()) { DrawTile(tile, graphicsObj, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles); } // get ram block data if (!m_ramDataValid) { m_ramDataValid = FPGATypes.GetRamBlockSize(m_view.TileRegex, out m_ramBlockWidth, out m_ramBlockHeight, out m_ramTiles); } foreach (Tile ramTile in m_ramTiles) { if (!m_view.TileRegex.IsMatch(ramTile.Location)) { continue; } DrawRAMTile(ramTile, graphicsObj, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles); } graphicsObj.Dispose(); }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); StringBuilder buffer = new StringBuilder(); buffer.AppendLine("################ GoAhead ################ GoAhead ################"); foreach (string netlistContainerName in NetlistContainerNames) { string anchor; List <XDLContainer> nlcs = new List <XDLContainer>(); nlcs.Add((XDLContainer)NetlistContainerManager.Instance.Get(netlistContainerName)); bool anchorFound = XDLContainer.GetAnchor(nlcs, out anchor); buffer.AppendLine("INST \"*inst_" + netlistContainerName + "\" LOC = \"" + anchor + "\"; # generated_by_GoAhead"); } // write to file if (File.Exists(FileName)) { TextWriter tw = new StreamWriter(FileName); tw.Write(buffer.ToString()); tw.Close(); } // write to gui OutputManager.WriteUCFOutput(buffer.ToString()); }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); if (TileSelectionManager.Instance.NumberOfSelectedTiles == 0) { OutputManager.WriteOutput("Warning: No tiles selected"); } // read file DesignParser parser = DesignParser.CreateDesignParser(XDLInFile); // into design NetlistContainer inContainer = new XDLContainer(); parser.ParseDesign(inContainer, this); // store selected parts in outDesign XDLContainer outContainer = (XDLContainer)inContainer.GetSelectedDesignElements(); // write design to file StreamWriter sw = new StreamWriter(XDLOutFile, false); outContainer.WriteCodeToFile(sw); sw.Close(); if (!string.IsNullOrEmpty(BinaryNetlist)) { SaveXDLLibraryElementAsBinaryLibraryElement saveCmd = new SaveXDLLibraryElementAsBinaryLibraryElement(); saveCmd.FileName = BinaryNetlist; saveCmd.XDLFileName = XDLOutFile; CommandExecuter.Instance.Execute(saveCmd); } }
protected override void DoCommandAction() { if (!TileSelectionManager.Instance.UserSelectionTypes.Any(s => s.Equals(UserSelectionType))) { throw new ArgumentException("UserSelectionType " + UserSelectionType + " does not exist"); } List <Tile> expansion = new List <Tile>(); foreach (Tile clb in TileSelectionManager.Instance.GetSelectedTiles().Where(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB))) { Tile interconnect = FPGATypes.GetInterconnectTile(clb); Port port = interconnect.SwitchMatrix.GetDrivenPorts().FirstOrDefault(p => p.Name.Equals(Begin)); bool startIsUserSelected = TileSelectionManager.Instance.IsUserSelected(interconnect.TileKey, UserSelectionType); bool continuePath = true; do { expansion.Add(interconnect); Location loc = Navigator.GetDestinations(interconnect, port).FirstOrDefault(l => l.Pip.Name.Equals(End)); if (loc == null) { throw new ArgumentException("Can not route via " + Begin + " from " + interconnect + " to " + End); } interconnect = loc.Tile; continuePath = (startIsUserSelected && TileSelectionManager.Instance.IsUserSelected(interconnect.TileKey, UserSelectionType)) || (!startIsUserSelected && !TileSelectionManager.Instance.IsUserSelected(interconnect.TileKey, UserSelectionType)); } while (continuePath); } expansion.ForEach(t => TileSelectionManager.Instance.AddToSelection(t.TileKey, false)); }
public static DesignParser CreateDesignParser(string fileName) { if (FPGA.FPGA.Instance.Family.Equals(FPGATypes.FPGAFamily.Undefined)) { throw new ArgumentException("Can not load design " + fileName + " as no FPGA is loaded. Use OpenBinFPGA to open a device description first."); } if (!File.Exists(fileName)) { throw new ArgumentException("File " + fileName + " not found"); } switch (Path.GetExtension(fileName).ToLower()) { case ".viv_nl": FPGATypes.AssertBackendType(FPGATypes.BackendType.Vivado); return(new TCLDesignParser(fileName)); case ".xdl": FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); return(new XDLDesignParser(fileName)); default: throw new ArgumentException("The extension of the argument FileName must be either xdl or viv_nl (case insensitive), but found " + Path.GetExtension(fileName)); } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); NetlistContainer netlistContainer = GetNetlistContainer(); // extract net names as we may not remve during iteration List <XDLNet> netNamesToDecompose = new List <XDLNet>(); foreach (string netName in NetNames) { XDLNet n = (XDLNet)netlistContainer.GetNet(netName); netNamesToDecompose.Add(n); } foreach (XDLNet net in netNamesToDecompose) { foreach (XDLPip pip in net.Pips) { XDLNet arc = new XDLNet(net.Name + "_" + pip.Location + "_" + pip.From + "_" + pip.To); // TODO what about attributes arc.Add(pip); netlistContainer.Add(arc); } net.ClearPips(); if (net.NetPinCount == 0) { netlistContainer.Remove(new Predicate <Net>(n => n.Name.Equals(net.Name))); } } }
protected override void DoCommandAction() { CheckParameters(); List <Tile> selectionCLB = new List <Tile>(); foreach (Tile t in TileSelectionManager.Instance.GetSelectedTiles().Where(tile => IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB))) { selectionCLB.Add(t); } List <Tile> selectionInt = new List <Tile>(); foreach (Tile clb in selectionCLB) { selectionInt.Add(FPGATypes.GetInterconnectTile(clb)); } foreach (Tile clb in selectionCLB) { Tile interconnect = FPGATypes.GetInterconnectTile(clb); foreach (Tuple <Port, Port> t in clb.SwitchMatrix.GetAllArcs().Where(a => Regex.IsMatch(a.Item2.Name, InputPortsRegex))) { foreach (Wire w in interconnect.WireList.Where(w => w.PipOnOtherTile.Equals(t.Item1.Name))) { interconnect.BlockPort(new FPGA.Port(w.LocalPip), Tile.BlockReason.ExcludedFromBlocking); } } } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado); LibElemInst inst = LibraryElementInstanceManager.Instance.GetInstantiation(InstanceName); LibraryElement libElement = Objects.Library.Instance.GetElement(inst.LibraryElementName); Tile anchorCLB = FPGA.FPGA.Instance.GetTile(inst.AnchorLocation); NetlistContainer netlistContainer = GetNetlistContainer(); switch (FPGA.FPGA.Instance.BackendType) { case FPGATypes.BackendType.ISE: RelocateInstancesForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer); RelocateNetsForXDL(libElement, anchorCLB, (XDLContainer)netlistContainer); // add design config if (AddDesignConfig && libElement.Containter is XDLContainer && ((XDLContainer)netlistContainer).GetDesignConfig().Length == 0) { ((XDLContainer)netlistContainer).AddDesignConfig(((XDLContainer)libElement.Containter).GetDesignConfig()); } break; case FPGATypes.BackendType.Vivado: RelocateInstancesForTCL(libElement, anchorCLB, (TCLContainer)netlistContainer); RelocateNetsForTCL(libElement, anchorCLB, netlistContainer); break; } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado); IEnumerable <string> clockRegions = FPGA.FPGA.Instance.GetAllTiles().Select(t => t.ClockRegion).Where(s => !string.IsNullOrEmpty(s)).Distinct().OrderBy(s => s); OutputManager.WriteOutput("# clock region wise resource report for " + FPGA.FPGA.Instance.DeviceName); OutputManager.WriteOutput("# the following clock regions will be reported " + string.Join(",", clockRegions)); OutputManager.WriteOutput("# "); List <SetColumnTypeNames> addCommandsForUnknownTypes = new List <SetColumnTypeNames>(); foreach (string clockRegion in clockRegions) { // get upper row int minX = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.X).Min(); int maxX = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.X).Max(); int minY = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.Y).Min(); int maxY = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Select(t => t.TileKey.Y).Max(); int tileCount = FPGA.FPGA.Instance.GetAllTiles().Where(t => t.ClockRegion.Equals(clockRegion)).Count(); OutputManager.WriteOutput("########################################################################################## "); OutputManager.WriteOutput("# report section for clock region " + clockRegion + " with " + tileCount + " tiles"); OutputManager.WriteOutput("# tiles contained in this clock region: " + string.Join(",", FPGA.FPGA.Instance.GetAllTiles().Select(t => t.Location))); for (int x = minX; x <= maxX; x++) { string resources = ""; for (int y = minY; y <= maxY; y++) { Tile t = FPGA.FPGA.Instance.GetTile(x, y); foreach (Slice s in t.Slices) { resources += s.SliceType + ","; } } if (resources.EndsWith(",")) { resources = resources.Remove(resources.Length - 1, 1); } SetColumnTypeNames addCmd = null; string typeName = Objects.ColumnTypeNameManager.Instance.GetColumnTypeNameByResource(resources, out addCmd); if (addCmd != null) { addCommandsForUnknownTypes.Add(addCmd); } OutputManager.WriteOutput("column=" + x + ",clock_region=" + clockRegion + ",type=" + typeName + ",resources=" + resources); } } OutputManager.WriteOutput("########################################################################################## "); OutputManager.WriteOutput("# for the columns with resource type unknown "); OutputManager.WriteOutput("# you might use the following commands in init.goa "); OutputManager.WriteOutput("# to provide a meaningful type name for that resource"); foreach (SetColumnTypeNames cmd in addCommandsForUnknownTypes) { OutputManager.WriteOutput("use " + cmd.ToString()); } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); XDLContainer nlc = (XDLContainer)GetNetlistContainer(); AddTemplate(nlc, Template, Location, PrimitiveIndex); }
protected override void DoCommandAction() { LibraryElement libElement = Objects.Library.Instance.GetElement(LibraryElementName); Tile anchor = FPGA.FPGA.Instance.GetTile(AnchorLocation); if (libElement.ResourceShape.Anchor.AnchorSliceNumber >= anchor.Slices.Count) { throw new ArgumentException("Too few slices on tile " + anchor.Location + ". Expecting " + libElement.ResourceShape.Anchor.AnchorSliceNumber + " but found " + anchor.Slices.Count + " slice."); } if (IdentifierManager.Instance.IsMatch(anchor.Location, IdentifierManager.RegexTypes.Interconnect)) { anchor = FPGATypes.GetCLTile(anchor).FirstOrDefault(); } if (AutoClearModuleSlot) { //this.FastAutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1)); AutoClearModuleSlotBeforeInstantiation(libElement, Enumerable.Repeat(anchor, 1)); } LibElemInst instantiation = new LibElemInst(); instantiation.AnchorLocation = AnchorLocation; instantiation.InstanceName = Hierarchy + InstanceName; instantiation.LibraryElementName = LibraryElementName; instantiation.SliceNumber = libElement.ResourceShape.Anchor.AnchorSliceNumber; instantiation.SliceName = anchor.Slices[(int)libElement.ResourceShape.Anchor.AnchorSliceNumber].SliceName; LibraryElementInstanceManager.Instance.Add(instantiation); // mark source as blocked ExcludeInstantiationSourcesFromBlocking markSrc = new ExcludeInstantiationSourcesFromBlocking(); markSrc.AnchorLocation = AnchorLocation; markSrc.LibraryElementName = LibraryElementName; CommandExecuter.Instance.Execute(markSrc); SaveLibraryElementInstantiation saveCmd = new SaveLibraryElementInstantiation(); saveCmd.AddDesignConfig = false; saveCmd.InsertPrefix = true; saveCmd.InstanceName = InstanceName; saveCmd.NetlistContainerName = NetlistContainerName; CommandExecuter.Instance.Execute(saveCmd); if (AutoFuse) { FuseNets fuseCmd = new FuseNets(); fuseCmd.NetlistContainerName = NetlistContainerName; fuseCmd.Mute = Mute; fuseCmd.Profile = Profile; fuseCmd.PrintProgress = PrintProgress; CommandExecuter.Instance.Execute(fuseCmd); } }
/// <summary> /// Relocate the tile given by instanceTileLocation from anchor /// instanceTileLocation does not have to be part of the FPGA /// </summary> /// <param name="instanceTileLocation"></param> /// <param name="anchor"></param> /// <returns></returns> /// public bool GetTargetLocation(string instanceTileLocation, Tile anchor, out string targetLocation) { targetLocation = ""; int x, y; FPGATypes.GetXYFromIdentifier(instanceTileLocation, out x, out y); int locationIncrX = x - ResourceShape.Anchor.AnchorLocationX; int locationIncrY = y - ResourceShape.Anchor.AnchorLocationY; int targetLocationX = anchor.LocationX + locationIncrX; int targetLocationY = anchor.LocationY + locationIncrY; // three chars should match the type CLB/BRAM/DSP if (string.IsNullOrEmpty(instanceTileLocation) || instanceTileLocation.Length < 3) { } string prefix = instanceTileLocation.Substring(0, 3); Tile targetTile = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => t.Location.StartsWith(prefix) && t.LocationX == targetLocationX && t.LocationY == targetLocationY); //int lastUnderScore = instanceTileLocation.LastIndexOf("_"); //targetLocation += instanceTileLocation.Substring(0, lastUnderScore); //targetLocation += "_X" + targetLocationX + "Y" + targetLocationY; // naming fun //String resolvedTargetLocation = null; //bool success = FPGA.FPGATypes.ResolveLMIdentifier(targetLocation, str => !FPGA.FPGA.Instance.Contains(str), out resolvedTargetLocation); if (targetTile != null) { targetLocation = targetTile.Location; return(true); } else { // relocated DSP INT_X3Y5 -> INT_BRAM_X3Y5 or INT_BRAM_BRK_X3Y5 // move to init.goa Tile differentlyNamedTile = FPGA.FPGA.Instance.GetAllTiles().Where(t => ((t.Location.StartsWith("BRAM_") && FPGA.FPGA.Instance.Family.Equals(FPGATypes.FPGAFamily.Virtex6)) || (t.Location.StartsWith("INT_BRAM_") && FPGA.FPGA.Instance.Family.Equals(FPGATypes.FPGAFamily.Spartan6))) && t.LocationX == targetLocationX && t.LocationY == targetLocationY).FirstOrDefault(); if (differentlyNamedTile != null) { targetLocation = differentlyNamedTile.Location; return(true); } else { targetLocation = ""; return(false); } //throw new ArgumentException("Error during relocation: Can not relocate " + instanceTileLocation + " using anchor " + anchor.Location + ". Target " + targetLocation + " not found"); } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); NetlistContainer netlistContainer = GetNetlistContainer(); foreach (XDLNet n in netlistContainer.Nets) { foreach (XDLPip pip in n.Pips) { Tile t = FPGA.FPGA.Instance.GetTile(pip.Location); if (!IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)) { continue; } foreach (Slice s in t.Slices) { bool inport = s.PortMapping.IsSliceInPort(new Port(pip.To)); bool outport = s.PortMapping.IsSliceOutPort(new Port(pip.To)); if ((inport | outport) && pip.To.Contains('_')) { NetPin pin = null; if (inport) { pin = new NetInpin(); } else { pin = new NetOutpin(); } string[] atoms = pip.To.Split('_'); pin.SlicePort = atoms[1]; if (netlistContainer.Instances.Any(i => i.SliceName.Equals(s.SliceName))) { // there should be only one instance on the slice XDLInstance inst = (XDLInstance)netlistContainer.Instances.First(i => i.SliceName.Equals(s.SliceName)); pin.InstanceName = inst.Name; } else { pin.InstanceName = s.SliceName; } bool pinExistsAlready = n.NetPins.FirstOrDefault(np => np.InstanceName.Equals(pin.InstanceName) && np.SlicePort.Equals(pin.SlicePort)) != null; if (!pinExistsAlready) { n.Add(pin); } } } } } }
private Tile GetCorner(string identifier, FPGATypes.Direction dir) { Tile tile = null; if (FPGA.FPGA.Instance.Contains(identifier)) { tile = FPGA.FPGA.Instance.GetTile(identifier); } else if (identifier.Contains("_")) { int split = identifier.IndexOf('_'); string prefix = identifier.Substring(0, split + 1); string suffix = identifier.Substring(split, identifier.Length - split); tile = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => t.Location.StartsWith(prefix) && t.Location.EndsWith(suffix)); // if we can not resolve the identifer, triggger error handling in Do if (tile == null) { return(null); } } else { return(null); } List <Tile> otherTiles = new List <Tile>(); otherTiles.Add(tile); // there might be more left interconnects if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.CLB)) { otherTiles.Add(FPGATypes.GetInterconnectTile(tile)); } else if (IdentifierManager.Instance.IsMatch(tile.Location, IdentifierManager.RegexTypes.Interconnect)) { foreach (Tile o in FPGATypes.GetCLTile(tile)) { otherTiles.Add(o); } } if (dir == FPGATypes.Direction.West) { int min = otherTiles.Min(t => t.TileKey.X); return(otherTiles.FirstOrDefault(t => t.TileKey.X == min)); } else if (dir == FPGATypes.Direction.East) { int max = otherTiles.Max(t => t.TileKey.X); return(otherTiles.FirstOrDefault(t => t.TileKey.X == max)); } else { throw new ArgumentException(GetType().Name + ".GetCorner only supports East and West"); } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); Slice where = FPGA.FPGA.Instance.Current.Slices[SliceNumber]; XDLMacroPort addedPort = new XDLMacroPort(PortName, new Port(PortString), where); XDLContainer netlistContainer = (XDLContainer)GetNetlistContainer(); netlistContainer.Add(addedPort); }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); NetlistContainer netlistContainer = GetNetlistContainer(); XDLNet net = (XDLNet )netlistContainer.GetNet(Netname); Regex filter = new Regex(PipRegexp, RegexOptions.Compiled); net.Remove(pip => filter.IsMatch(pip.ToString())); }
private void DrawRAMTile(Tile ramTile, Graphics graphicsObj, bool addIncrementForSelectedTiles, bool addIncrementForUserSelectedTiles) { int x = -1; int y = -1; switch (FPGA.FPGA.Instance.Family) { case FPGATypes.FPGAFamily.Artix7: case FPGATypes.FPGAFamily.Kintex7: case FPGATypes.FPGAFamily.Virtex7: case FPGATypes.FPGAFamily.Zynq: { if (FPGATypes.IsOrientedMatch(ramTile.Location, IdentifierManager.RegexTypes.BRAM_left)) { // ram tile are in the bottom middle x = ramTile.TileKey.X; y = ramTile.TileKey.Y - (m_ramBlockHeight - 1); } else //if (Regex.IsMatch(ramTile.Location, "_R_")) { // ram tile are in the bottom middle x = ramTile.TileKey.X - (m_ramBlockWidth - 1); y = ramTile.TileKey.Y - (m_ramBlockHeight - 1); } break; } default: { // ram tile are in the bottom right x = ramTile.TileKey.X - (m_ramBlockWidth - 1); y = ramTile.TileKey.Y - (m_ramBlockHeight - 1); break; } } if (FPGA.FPGA.Instance.Contains(x, y)) { Tile upperLeft = FPGA.FPGA.Instance.GetTile(x, y); int upperLeftX = upperLeft.TileKey.X * m_view.TileSize; int upperLeftY = upperLeft.TileKey.Y * m_view.TileSize; Rectangle rect = new Rectangle(); rect.X = upperLeftX - 1; rect.Y = upperLeftY - 1; rect.Width = (m_ramBlockWidth * (m_view.TileSize - 1) + m_ramBlockWidth - 1) - 2; rect.Height = (m_ramBlockHeight * (m_view.TileSize - 1) + m_ramBlockHeight) - 2; m_sb.Color = m_view.GetColor(ramTile, addIncrementForSelectedTiles, addIncrementForUserSelectedTiles); graphicsObj.FillRectangle(m_sb, rect); } }
protected override void DoCommandAction() { Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)); Tile interconnect = FPGATypes.GetInterconnectTile(clb); List <string> lutInPorts = new List <string>(); foreach (Port lutInPort in clb.SwitchMatrix.Ports.Where(p => Regex.IsMatch(p.Name, LUTInPortFilter))) { lutInPorts.Add(lutInPort.Name); } Adjacency adjacency = new Adjacency(lutInPorts, EndPortFilter, LUTOutPortFilter); // section 1 foreach (Port endPort in interconnect.SwitchMatrix.Ports.Where(p => Regex.IsMatch(p.Name, EndPortFilter)).OrderBy(p => p.Name[p.Name.Length - 1])) { foreach (Port logicIn in interconnect.SwitchMatrix.GetDrivenPorts(endPort)) { // goto CLB foreach (Location loc in Navigator.GetDestinations(interconnect, logicIn).Where(l => l.Tile.Location.Equals(clb.Location))) { foreach (Port lutInPort in clb.SwitchMatrix.GetDrivenPorts(loc.Pip).Where(l => Regex.IsMatch(l.Name, LUTInPortFilter))) { adjacency.AddConnection(endPort.Name, lutInPort.Name); } } } } // section 2 foreach (Port lutOutPort in clb.SwitchMatrix.Ports.Where(p => Regex.IsMatch(p.Name, LUTOutPortFilter))) { foreach (Port logicOut in clb.SwitchMatrix.GetDrivenPorts(lutOutPort)) { // goto int foreach (Location locInt in Navigator.GetDestinations(clb, logicOut).Where(l => l.Tile.Location.Equals(interconnect.Location))) { foreach (Port logicIn in interconnect.SwitchMatrix.GetDrivenPorts(locInt.Pip)) { foreach (Location locClb in Navigator.GetDestinations(interconnect, logicIn).Where(l => l.Tile.Location.Equals(clb.Location))) { foreach (Port lutInPort in clb.SwitchMatrix.GetDrivenPorts(locClb.Pip).Where(l => Regex.IsMatch(l.Name, LUTInPortFilter))) { adjacency.AddConnection(lutOutPort.Name, lutInPort.Name); } } } } } } OutputManager.WriteOutput(adjacency.ToString()); }
private LibraryElement GetFF(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort) { LibraryElement el = new LibraryElement(); el.SliceNumber = SliceNumber; el.Name = belName; el.PrimitiveName = BELType; el.BEL = belName; el.LoadCommand = ToString(); el.Containter = new NetlistContainer(); el.VHDLGenericMap = "generic map ( INIT => '0' )"; el.Containter = new XDLModule(); el.VivadoConnectionPrimitive = true; // Q output XDLPort q = new XDLPort(); q.Direction = FPGATypes.PortDirection.Out; q.ExternalName = "Q"; q.InstanceName = "unknown"; q.SlicePort = "unknown"; el.Containter.Add(q); List <string> inputs = new List <string>(); inputs.Add("D"); inputs.Add("C"); inputs.Add("CE"); inputs.Add("R"); foreach (string i in inputs) { XDLPort p = new XDLPort(); p.Direction = FPGATypes.PortDirection.In; p.ExternalName = i; p.InstanceName = "unknown"; p.SlicePort = "unknown"; p.ConstantValuePort = false; el.Containter.Add(p); } ; Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)); Tile interconnect = FPGATypes.GetInterconnectTile(clb); foreach (string stopOverPortName in StopOverPorts) { el.AddPortToBlock(interconnect, new Port(stopOverPortName)); } return(el); }
public XDLFile(bool exportPortDeclarations, bool exportDummyNets, List <XDLContainer> netlistContainerNames, bool includeDesignStatement, bool includeModuleHeader, bool includeModuleFooter, string designName, bool sortInstancesBySliceName) { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); m_exportPortDeclarations = exportPortDeclarations; m_exportDummyNets = exportDummyNets; m_netlistContainer = netlistContainerNames; m_includeDesignStatement = includeDesignStatement; m_includeModuleHeader = includeModuleHeader; m_includeModuleFooter = includeModuleFooter; m_designName = designName; }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); // read file DesignParser parser = DesignParser.CreateDesignParser(FileName); XDLContainer container = new XDLContainer(); // into design parser.ParseDesign(container, this); // derive name from file string elementName = Path.GetFileNameWithoutExtension(FileName); if (container.ModuleCount != 0) { // find ports to block and assign them to slices // as we want to either // connect these ports (if used) or // drive a '1' to (if unused) foreach (XDLModule module in container.Modules) { // new library element to be added to library LibraryElement libElement = new LibraryElement(); libElement.Containter = module; libElement.Name = elementName; libElement.PrimitiveName = elementName; libElement.LoadCommand = ToString(); // add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library Objects.Library.Instance.Add(libElement); DeriveBlockingData(libElement); } } else { // new library element to be added to library LibraryElement libElement = new LibraryElement(); libElement.Containter = container; libElement.Name = elementName; libElement.PrimitiveName = elementName; libElement.LoadCommand = ToString(); // add lib element to library, BEFORE deriving block data as command SaveXDLLibraryElementAsBinaryLibraryElement access the element in the library Objects.Library.Instance.Add(libElement); DeriveBlockingData(libElement); } }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado); switch (FPGA.FPGA.Instance.BackendType) { case FPGATypes.BackendType.ISE: CutOffISE(); break; case FPGATypes.BackendType.Vivado: CutOffVivado(); break; } }
private XDLPort ExtractPort(string portCode) { // extract port string[] atoms = Regex.Split(portCode, @"\s+"); XDLPort port = new XDLPort(); port.ExternalName = Regex.Replace(atoms[1], "\"", ""); port.InstanceName = Regex.Replace(atoms[2], "\"", ""); port.SlicePort = Regex.Replace(atoms[3], "\"", ""); port.SlicePort = Regex.Replace(port.SlicePort, ";", ""); port.Direction = FPGATypes.GetDirection(new Port(port.SlicePort)); return(port); }
private LibraryElement GetLUT(string belName, bool makeInputsConstant, string inputPortPrefix, string outputPort, string initValue) { int lutSize = 6; LibraryElement el = new LibraryElement(); el.SliceNumber = SliceNumber; el.Name = belName; el.PrimitiveName = BELType; el.BEL = belName; el.LoadCommand = ToString(); el.Containter = new NetlistContainer(); el.VHDLGenericMap = "generic map ( INIT => X\"" + initValue + "\" )"; el.Containter = new XDLModule(); el.VivadoConnectionPrimitive = true; // one output per LUT XDLPort outPort = new XDLPort(); outPort.Direction = FPGATypes.PortDirection.Out; outPort.ExternalName = "O"; outPort.InstanceName = "unknown"; outPort.SlicePort = "unknown"; el.Containter.Add(outPort); // six inputs I=..I5 for (int i = 0; i < lutSize; i++) { AddXDLPort(el, "I", i, FPGATypes.PortDirection.In, makeInputsConstant); } Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)); Tile interconnect = FPGATypes.GetInterconnectTile(clb); List <string> lutPortNames = new List <string>(); // see LUTRouting tab for (int i = 1; i <= lutSize; i++) { lutPortNames.Add(inputPortPrefix + i); } foreach (string stopOverPortName in StopOverPorts) { el.AddPortToBlock(interconnect, new Port(stopOverPortName)); } return(el); }
private List <Command> GetTunnelCommands(FPGATypes.InterfaceDirection direction, List <Command> placementCommands) { List <Command> result = new List <Command>(); // TODO make parameter? foreach (Command placeCmd in placementCommands.Where(c => c is AddSingleInstantiationByTile)) { AddSingleInstantiationByTile addCmd = (AddSingleInstantiationByTile)placeCmd; Tile clb = FPGA.FPGA.Instance.GetTile(addCmd.AnchorLocation); Tile interconnect = FPGATypes.GetInterconnectTile(clb); ExcludePortsFromBlockingOnTileByRegexp exclude = new ExcludePortsFromBlockingOnTileByRegexp(); exclude.CheckForExistence = false; exclude.IncludeAllPorts = false; exclude.Location = interconnect.Location; if (BuildTarget == Target.Static && direction == FPGATypes.InterfaceDirection.East) { exclude.PortNameRegexp = "(WW2E[0|1|2|3])|(EE2B[0|1|2|3])"; } else if (BuildTarget == Target.Static && direction == FPGATypes.InterfaceDirection.West) { exclude.PortNameRegexp = "(EE2E[0|1|2|3])|(WW2B[0|1|2|3])"; } else if (BuildTarget == Target.Module && direction == FPGATypes.InterfaceDirection.East) { exclude.PortNameRegexp = "(EE2E[0|1|2|3])|(WW2B[0|1|2|3])"; } else if (BuildTarget == Target.Module && direction == FPGATypes.InterfaceDirection.West) { exclude.PortNameRegexp = "(WW2E[0|1|2|3])|(EE2B[0|1|2|3])"; } else { throw new ArgumentException("Direction " + direction + " not implemented"); } //exclude.PortNameRegexp = "((EE)|(WW))2(B|E)[0|1|2|3]"; // the epxression parser cant handle [0-3] if (result.Count == 0) { exclude.Comment = " exclude tunnel wires from blocking"; } result.Add(exclude); } return(result); }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE, FPGATypes.BackendType.Vivado); switch (FPGA.FPGA.Instance.BackendType) { case FPGATypes.BackendType.ISE: PrintAreaGroupForISE(); break; case FPGATypes.BackendType.Vivado: PrintAreaGroupForVivado(); break; default: break; } }
protected override void DoCommandAction() { // Vivado only FPGATypes.AssertBackendType(FPGATypes.BackendType.Vivado); TCLContainer nlc = (TCLContainer)GetNetlistContainer(); bool closeStream = false; if (m_sw == null) { // do not close external stream closeStream = true; m_sw = new StreamWriter(FileName, false); } WriteHeader(nlc, m_sw); if (IncludeLinkDesignCommand) { //this.m_sw.WriteLine("link_design -name empty_netlist -part " + FPGA.FPGA.Instance.DeviceName); } // eingelesen aus Netzliste (also von Vivado erstellt!) genrieren (brauchen wir erstmal nicht, nur fuer eigene instanzen ggf neu Hierstufen ienziehen, siehe create_cell) //this.WriteHierarchyCells(nlc); WriteInstances(nlc); //this.WritePins(nlc); ////this.WritePorts(nlc); WriteNets(nlc); m_sw.WriteLine(""); m_sw.WriteLine("# end of file"); if (closeStream) { m_sw.Close(); } }
private void InitLUTRouting() { m_grdViewLUTRouting.Rows.Clear(); // LUT routing requires wire lists if (FPGA.FPGA.Instance.WireListCount == 0) { return; } if (IdentifierManager.Instance.IsMatch(m_tile.Location, IdentifierManager.RegexTypes.CLB)) { Regex filter1 = null; Regex filter2 = null; Regex filter3 = null; Regex filter4 = null; bool filter1Valid = false; bool filter2Valid = false; bool filter3Valid = false; bool filter4Valid = false; GetFilter(m_txtLRLutOutFilter.Text, out filter1, out filter1Valid); GetFilter(m_txtLREndFilter.Text, out filter2, out filter2Valid); GetFilter(m_txtLRBegFilter.Text, out filter3, out filter3Valid); GetFilter(m_txtLRLUTInFilter.Text, out filter4, out filter4Valid); if (!filter1Valid || !filter2Valid || !filter3Valid || !filter4Valid) { return; } foreach (LUTRoutingInfo info in FPGATypes.GetLUTRouting(m_tile)) { string port1 = info.Port1 != null ? info.Port1.Name : ""; string port2 = info.Port2 != null ? info.Port2.Name : ""; string port3 = info.Port3 != null ? info.Port3.Name : ""; string port4 = info.Port4 != null ? info.Port4.Name : ""; if (filter1.IsMatch(port1) && filter2.IsMatch(port2) && filter3.IsMatch(port3) && filter4.IsMatch(port4)) { m_grdViewLUTRouting.Rows.Add(port1, port2, port3, port4); } } } }
private LibraryElement GetBEL(BELInfo info) { LibraryElement element = new LibraryElement { SliceNumber = SliceNumber, Name = info.belName, PrimitiveName = BELType, BEL = info.belName, LoadCommand = ToString(), Containter = new XDLModule(), VHDLGenericMap = info.type.VHDLGenericMap, VivadoConnectionPrimitive = true }; // Outputs foreach (string output in info.type.outputNames) { element.Containter.Add(MakeXDLPort(output, FPGATypes.PortDirection.Out)); } // Inputs foreach (string input in info.type.inputNames) { element.Containter.Add(MakeXDLPort(input, FPGATypes.PortDirection.In, info.type.inputsConstantValue)); } // Get first encountered clb ?! Tile clb = FPGA.FPGA.Instance.GetAllTiles().FirstOrDefault(t => IdentifierManager.Instance.IsMatch(t.Location, IdentifierManager.RegexTypes.CLB)); Tile interconnect = FPGATypes.GetInterconnectTile(clb); if (info.traverseBackwards) { TraverseBackwards(element, clb, interconnect, info); } foreach (string stopOverPortName in StopOverPorts) { element.AddPortToBlock(interconnect, new Port(stopOverPortName)); } return(element); }
protected override void DoCommandAction() { FPGATypes.AssertBackendType(FPGATypes.BackendType.ISE); XDLContainer netlistContainer = (XDLContainer)GetNetlistContainer(); Port from = new Port(From); Port to = new Port(To); if (!FPGA.FPGA.Instance.Current.SwitchMatrix.Contains(from, to)) { throw new ArgumentException("Tile " + FPGA.FPGA.Instance.Current + " does not contain arc " + from + " -> " + to); } if (FPGA.FPGA.Instance.Current.IsPortBlocked(from) && !((XDLNet)netlistContainer.LastNetAdded).Contains(FPGA.FPGA.Instance.Current, from)) { throw new ArgumentException("Port " + from + " on slice " + FPGA.FPGA.Instance.Current + " is blocked by another net"); } if (FPGA.FPGA.Instance.Current.IsPortBlocked(to) && !((XDLNet)netlistContainer.LastNetAdded).Contains(FPGA.FPGA.Instance.Current, to)) { throw new ArgumentException("Port " + to + " on slice " + FPGA.FPGA.Instance.Current + " is blocked by another net"); } if (netlistContainer == null) { throw new ArgumentException("No current macro"); } if (netlistContainer.LastNetAdded == null) { throw new ArgumentException("No current net"); } ((XDLNet)netlistContainer.LastNetAdded).Add(FPGA.FPGA.Instance.Current, from, to); if (!FPGA.FPGA.Instance.Current.IsPortBlocked(from)) { FPGA.FPGA.Instance.Current.BlockPort(from, Tile.BlockReason.Blocked); } if (!FPGA.FPGA.Instance.Current.IsPortBlocked(to)) { FPGA.FPGA.Instance.Current.BlockPort(to, Tile.BlockReason.Blocked); } }