int memory_init()
{
int i, cpu;
MHELE hardware;
int abits1, abits2, abits3, abitsmin;
rdelement_max = 0;
wrelement_max = 0;
rdhard_max = HT_USER;
wrhard_max = HT_USER;
for (cpu = 0; cpu < MAX_CPU; cpu++)
cur_mr_element[cpu] = cur_mw_element[cpu] = null;
ophw = 0xff;
/* ASG 980121 -- allocate external memory */
if (memory_allocate_ext() == 0)
return 0;
for (cpu = 0; cpu < cpu_gettotalcpu(); cpu++)
{
setOPbasefunc[cpu] = null;
ramptr[cpu] = romptr[cpu] = memory_region(REGION_CPU1 + cpu);
/* initialize the memory base pointers for memory hooks */
int _mra = 0;
if (Machine.drv.cpu[cpu].memory_read != null && Machine.drv.cpu[cpu].memory_read[_mra] != null)
{
while (Machine.drv.cpu[cpu].memory_read[_mra].start != -1)
{
// if (_mra.base) *_mra.base = memory_find_base (cpu, _mra.start);
// if (_mra.size) *_mra.size = _mra.end - _mra.start + 1;
_mra++;
}
}
int _mwa = 0;
if (Machine.drv.cpu[cpu].memory_write != null && Machine.drv.cpu[cpu].memory_write[_mwa] != null)
{
while (Machine.drv.cpu[cpu].memory_write[_mwa].start != -1)
{
if (Machine.drv.cpu[cpu].memory_write[_mwa]._base != null)
{
_BytePtr b = memory_find_base(cpu, Machine.drv.cpu[cpu].memory_write[_mwa].start);
Machine.drv.cpu[cpu].memory_write[_mwa]._base.buffer = b.buffer;
Machine.drv.cpu[cpu].memory_write[_mwa]._base.offset = b.offset;
}
if (Machine.drv.cpu[cpu].memory_write[_mwa].size != null)
{
Machine.drv.cpu[cpu].memory_write[_mwa].size[0] = Machine.drv.cpu[cpu].memory_write[_mwa].end - Machine.drv.cpu[cpu].memory_write[_mwa].start + 1;
}
_mwa++;
}
}
/* initialize port structures */
readport_size[cpu] = 0;
writeport_size[cpu] = 0;
readport[cpu] = null;
writeport[cpu] = null;
/* install port handlers - at least an empty one */
int ioread = 0;
if (Machine.drv.cpu[cpu].port_read == null) Machine.drv.cpu[cpu].port_read = empty_readport;
while (true)
{
if (install_port_read_handler_common(cpu, Machine.drv.cpu[cpu].port_read[ioread].start, Machine.drv.cpu[cpu].port_read[ioread].end, Machine.drv.cpu[cpu].port_read[ioread].handler, 0) == null)
{
memory_shutdown();
return 0;
}
if (Machine.drv.cpu[cpu].port_read[ioread].start == -1) break;
ioread++;
}
int iowrite = 0;
if (Machine.drv.cpu[cpu].port_write == null) Machine.drv.cpu[cpu].port_write = empty_writeport;
while (true)
{
if (install_port_write_handler_common(cpu, Machine.drv.cpu[cpu].port_write[iowrite].start, Machine.drv.cpu[cpu].port_write[iowrite].end, Machine.drv.cpu[cpu].port_write[iowrite].handler, 0) == null)
{
memory_shutdown();
return 0;
}
if (Machine.drv.cpu[cpu].port_write[iowrite].start == -1) break;
iowrite++;
}
portmask[cpu] = 0xffff;
#if HAS_Z80
if ((Machine.drv.cpu[cpu].cpu_type & ~CPU_FLAGS_MASK) == CPU_Z80 &&
(Machine.drv.cpu[cpu].cpu_type & CPU_16BIT_PORT) == 0)
portmask[cpu] = 0xff;
#endif
}
/* initialize grobal handler */
for (i = 0; i < MH_HARDMAX; i++)
{
memoryreadoffset[i] = 0;
memorywriteoffset[i] = 0;
}
/* bank memory */
for (i = 1; i <= MAX_BANKS; i++)
{
memoryreadhandler[i] = bank_read_handler[i];
memorywritehandler[i] = bank_write_handler[i];
}
/* non map memory */
memoryreadhandler[HT_NON] = mrh_error;
memorywritehandler[HT_NON] = mwh_error;
/* NOP memory */
memoryreadhandler[HT_NOP] = mrh_nop;
memorywritehandler[HT_NOP] = mwh_nop;
/* RAMROM memory */
memorywritehandler[HT_RAMROM] = mwh_ramrom;
/* ROM memory */
memorywritehandler[HT_ROM] = mwh_rom;
/* if any CPU is 21-bit or more, we change the error handlers to be more benign */
for (cpu = 0; cpu < cpu_gettotalcpu(); cpu++)
if (ADDRESS_BITS(cpu) >= 21)
{
memoryreadhandler[HT_NON] = mrh_error_sparse;
memorywritehandler[HT_NON] = mwh_error_sparse;
#if HAS_TMS34010
if ((Machine.drv.cpu[cpu].cpu_type & ~CPU_FLAGS_MASK)==CPU_TMS34010)
{
memoryreadhandler[HT_NON] = mrh_error_sparse_bit;
memorywritehandler[HT_NON] = mwh_error_sparse_bit;
}
#endif
}
for (cpu = 0; cpu < cpu_gettotalcpu(); cpu++)
{
/* cpu selection */
abits1 = (int)ABITS1(cpu);
abits2 = (int)ABITS2(cpu);
abits3 = (int)ABITS3(cpu);
abitsmin = (int)ABITSMIN(cpu);
/* element shifter , mask set */
mhshift[cpu, 0] = (abits2 + abits3);
mhshift[cpu, 1] = abits3; /* 2nd */
mhshift[cpu, 2] = 0; /* 3rd (used by set_element)*/
mhmask[cpu, 0] = (int)MHMASK(abits1); /*1st(used by set_element)*/
mhmask[cpu, 1] = (int)MHMASK(abits2); /*2nd*/
mhmask[cpu, 2] = (int)MHMASK(abits3); /*3rd*/
/* allocate current element */
if ((cur_mr_element[cpu] = new MHELE[sizeof(MHELE) << abits1]) == null)
{
memory_shutdown();
return 0;
}
if ((cur_mw_element[cpu] = new MHELE[sizeof(MHELE) << abits1]) == null)
{
memory_shutdown();
return 0;
}
/* initialize curent element table */
for (i = 0; i < (1 << abits1); i++)
{
cur_mr_element[cpu][i] = HT_NON; /* no map memory */
cur_mw_element[cpu][i] = HT_NON; /* no map memory */
}
//memoryread = Machine.drv.cpu[cpu].memory_read;
//memorywrite = Machine.drv.cpu[cpu].memory_write;
/* memory read handler build */
if (Machine.drv.cpu[cpu].memory_read != null)
{
int mra = 0;
while (Machine.drv.cpu[cpu].memory_read[mra].start != -1) mra++;
mra--;
while (mra >= 0)
{
mem_read_handler handler = Machine.drv.cpu[cpu].memory_read[mra].handler;
int _handler = Machine.drv.cpu[cpu].memory_read[mra]._handler;
switch (_handler)
{
case MRA_RAM:
case MRA_ROM:
hardware = HT_RAM; /* sprcial case ram read */
break;
case MRA_BANK1:
case MRA_BANK2:
case MRA_BANK3:
case MRA_BANK4:
case MRA_BANK5:
case MRA_BANK6:
case MRA_BANK7:
case MRA_BANK8:
case MRA_BANK9:
case MRA_BANK10:
case MRA_BANK11:
case MRA_BANK12:
case MRA_BANK13:
case MRA_BANK14:
case MRA_BANK15:
case MRA_BANK16:
{
hardware = (byte)((int)MRA_BANK1 - (int)_handler + 1);
memoryreadoffset[hardware] = bankreadoffset[hardware] = Machine.drv.cpu[cpu].memory_read[mra].start;
cpu_bankbase[hardware] = memory_find_base(cpu, Machine.drv.cpu[cpu].memory_read[mra].start);
break;
}
case MRA_NOP:
hardware = HT_NOP;
break;
default:
/* create newer hardware handler */
if (rdhard_max == MH_HARDMAX)
{
printf("read memory hardware pattern over !\n");
hardware = 0;
}
else
{
/* regist hardware function */
hardware = (byte)rdhard_max++;
memoryreadhandler[hardware] = handler;
memoryreadoffset[hardware] = Machine.drv.cpu[cpu].memory_read[mra].start;
}
break;
}
/* hardware element table make */
set_element(cpu, new _BytePtr(cur_mr_element[cpu]),
(int)(((uint)Machine.drv.cpu[cpu].memory_read[mra].start) >> abitsmin),
(int)(((uint)Machine.drv.cpu[cpu].memory_read[mra].end) >> abitsmin),
hardware, new _BytePtr(readhardware), ref rdelement_max);
mra--;
}
}
/* memory write handler build */
if (Machine.drv.cpu[cpu].memory_write != null)
{
int mwa = 0;
while (Machine.drv.cpu[cpu].memory_write[mwa].start != -1) mwa++;
mwa--;
while (mwa >= 0)
{
mem_write_handler handler = Machine.drv.cpu[cpu].memory_write[mwa].handler;
int _handler = Machine.drv.cpu[cpu].memory_write[mwa]._handler;
switch (_handler)
{
case MWA_RAM:
hardware = HT_RAM; /* sprcial case ram write */
break;
case MWA_BANK1:
case MWA_BANK2:
case MWA_BANK3:
case MWA_BANK4:
case MWA_BANK5:
case MWA_BANK6:
case MWA_BANK7:
case MWA_BANK8:
case MWA_BANK9:
case MWA_BANK10:
case MWA_BANK11:
case MWA_BANK12:
case MWA_BANK13:
case MWA_BANK14:
case MWA_BANK15:
case MWA_BANK16:
{
hardware = (byte)((int)MWA_BANK1 - (int)_handler + 1);
memorywriteoffset[hardware] = bankwriteoffset[hardware] = Machine.drv.cpu[cpu].memory_write[mwa].start;
cpu_bankbase[hardware] = memory_find_base(cpu, Machine.drv.cpu[cpu].memory_write[mwa].start);
break;
}
case MWA_NOP:
hardware = HT_NOP;
break;
case MWA_RAMROM:
hardware = HT_RAMROM;
break;
case MWA_ROM:
hardware = HT_ROM;
break;
default:
/* create newer hardware handler */
if (wrhard_max == MH_HARDMAX)
{
printf("write memory hardware pattern over !\n");
hardware = 0;
}
else
{
/* regist hardware function */
hardware = (byte)wrhard_max++;
memorywritehandler[hardware] = handler;
memorywriteoffset[hardware] = Machine.drv.cpu[cpu].memory_write[mwa].start;
}
break;
}
/* hardware element table make */
set_element(cpu, new _BytePtr(cur_mw_element[cpu]),
(int)(((uint)Machine.drv.cpu[cpu].memory_write[mwa].start) >> abitsmin),
(int)(((uint)Machine.drv.cpu[cpu].memory_write[mwa].end) >> abitsmin),
hardware, new _BytePtr(writehardware), ref wrelement_max);
mwa--;
}
}
}
return 1; /* ok */
}
static void set_element(int cpu, _BytePtr celement, int sp, int ep, MHELE type, _BytePtr subelement, ref int ele_max)
{
int i;
int edepth = 0;
int shift, mask;
_BytePtr eele = celement;
_BytePtr sele = celement;
_BytePtr ele;
int ss, sb, eb, ee;
if ((uint)sp > (uint)ep) return;
do
{
mask = mhmask[cpu, edepth];
shift = mhshift[cpu, edepth];
/* center element */
ss = (int)((uint)sp >> shift);
sb = (int)((uint)sp != 0 ? ((uint)(sp - 1) >> shift) + 1 : 0);
eb = (int)(((uint)(ep + 1) >> shift) - 1);
ee = (int)((uint)ep >> shift);
if (sb <= eb)
{
if ((sb | mask) == (eb | mask))
{
/* same reasion */
ele = (sele != null ? sele : eele);
for (i = sb; i <= eb; i++)
{
ele[i & mask] = type;
}
}
else
{
if (sele != null) for (i = sb; i <= (sb | mask); i++)
sele[i & mask] = type;
if (eele != null) for (i = eb & (~mask); i <= eb; i++)
eele[i & mask] = type;
}
}
edepth++;
if (ss == sb) sele = null;
else sele = get_element(sele, ss & mask, mhmask[cpu, edepth],
subelement, ref ele_max);
if (ee == eb) eele = null;
else eele = get_element(eele, ee & mask, mhmask[cpu, edepth],
subelement, ref ele_max);
} while (sele != null || eele != null);
}
public static void cpu_setbank(int bank, _BytePtr _base)
{
if (bank >= 1 && bank <= MAX_BANKS)
{
cpu_bankbase[bank] = _base;
if (ophw == bank)
{
ophw = 0xff;
cpu_setOPbase16((int)cpu_get_pc(), 0);
}
}
}
