NaturalDocs with support for Verilog, SystemVerilog, and VHDL
Currently supporting:
- Verilog (WIP)
- SystemVerilog (WIP)
- Supports Modules
- Ports as a 'parameter' list
- Modports under interface "class"
- Modules with hierarchy
- Modules page
- Interfaces page
- VHDL
Natural Docs is an open source documentation generator for multiple programming languages. You document your code in a natural syntax that reads like plain English. Natural Docs then scans your code and builds high-quality HTML documentation from it.
More information is available on NaturalDocs.org, including:
You can also join the community:
Natural Docs is licensed under the GNU Affero General Public License, version 3. See Engine\Resources\License\License.txt for full details and incorporated code.